UB06 Session 6

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Date: Wednesday, March 27, 2019
Time: 12:00 - 14:00
Location / Room:

LabelPresentation Title
Authors
UB06.1TIMING & POWER CHARACTERIZATION FRAMEWORK FOR EMBEDDED PROCESSORS
Authors:
Mark Kettner and Frank Oppenheimer, OFFIS - Institute for Information Technology, DE
Abstract
We present a framework that significantly reduces the effort for creating accurate energy/timing models for embedded processors covering different conditions (e.g. varying temperature and clock frequency). It supports the systematic collection of large amount of timing and power data needed to cover the complete microprocessors' ISA in different working conditions. Since manual measurements are tedious and error-prone we present an automated approach. The physical setup consists of a processor board, a power measurement device, a heating element and a logic analyser observing the processor's GPIOs. The software consists of a code-generator for characterization binaries, a control program which orchestrates the physical setup and the evaluation software which generates the desired timing and power data. We will demonstrate this framework for an ARM Cortex-M microcontroller and present interesting and even undocumented behaviour while using certain CPU and FPU features.

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UB06.2EDP PLAYER: A DESIGN ASSISTANT FOR PROCEDURAL DESIGN AUTOMATION OF ANALOG INTEGRATED CIRCUITS
Authors:
Matthias Schweikardt1, Husni Habal2 and Jürgen Scheible1
1Hochschule Reutlingen, DE; 2Infineon Technologies, DE
Abstract
In this demonstration, we address procedural circuit design automation of analog integrated circuits. Procedural automation means, that the knowledge-based strategy of human experts is captured in an executable script, which makes it reusable. We call this principle EDP (Expert Design Plan). An EDP can cover different performance parameters, technologies and topologies. We present the EDP Player, which enables the creation and execution of plain EDPs. The tool provides a preliminary version of an instruction set tailored to the typical manual analog circuit design flow, called EDPL (EDP-Language). The tool is fully integrated within Cadence Virtuoso based on Cadence SKILL. The tool has been utilized for three different examples: the automated design of a miller operational amplifier, a bandgap, and the automated creation of variants of a smart power IC. The usage of EDPs leads to a strong reduction of design time without loss of both design quality and reliability.

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UB06.3MICROPLAN: MICRO-SYSTEM DESIGN AND PRODUCTION PLANNING TOOL
Authors:
Horst Tilman, Robert Fischbach and Jens Lienig, Technische Universität Dresden, DE
Abstract
We present a tool that enables to layout and plan the production of heterogeneous micro-systems. The tool consists of a simple layout editor, a visualization of the wafer utilization and eventually a calculation of the production cost for a given order quantity. Being superior with regard to performance, heterogeneous systems are often rendered unviable due to high production costs. However, using our tool allows users to design heterogeneous systems with an emphasis on low production costs. The tool is developed within the MICROPRINCE project and in close cooperation with X-Fab. The tool doesn't require installation and can be used by any visitor on their smartphone or computer.

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UB06.4MROS AND ZYTLEBOT: DESIGN PLATFORMS FOR EMBEDDED ROBOT SYSTEMS
Authors:
Hideki Takase1, Yasuhiro Nitta1 and So Tamura2
1Kyoto University, JP; 2Kyoto Universiy, JP
Abstract
We are researching design platforms for robot systems based on ROS (Robot Operating System). In the booth, we will present the current status of two research activities. The first project is mROS, a lightweight runtime environment of ROS nodes. mROS offers a ROS-compatible communication library to be operated on the embedded mid-range processor which cannot be operated with Linux. mROS contributes to utilizing low power embedded devices into the ROS system. We will show the case study of mROS on the distributed camera system. The second is ZytleBot, an autonomous driving robot as an FPGA integrated platform utilizing the Xilinx programmable SoC. In ZytleBot, the FPGA performs preprocessing of the road surface image acquired from the camera and calculation of HOG feature calculation for signal detection. We achieved about 5 times faster performance by utilizing the FPGA. We will demonstrate the real-time signal detection task on the ZytleBot that won FPT'18 FPGA design competition.

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UB06.5PREESM: GENERATING ENERGY-OPTIMIZED ADAPTIVE SOFTWARE ON A HETEROGENEOUS PLATFORM WITH PREESM
Authors:
Maxime Pelcat1, Karol Desnos1, Daniel Menard1, Florian Arrestier1, Alexandre Honorat1, Claudio Rubattu2, Antoine Morvan1, Julien Heulot1 and Jean-François Nezan1
1INSA Rennes/IETR, FR; 2UNISS, INSA Rennes/IETR, FR
Abstract
This Booth demonstrates how PREESM and SPIDER tools generate energy-optimized sensor-based adaptive software on a heterogeneous platform. PREESM is a rapid system prototyping tool provided with a runtime manager named SPIDER. PREESM simulates stream processing applications and generates code for multi/many-cores. Processing can either be statically mapped or adaptively managed by SPIDER. Steps when using PREESM are: 1- Model your Application: PREESM provides you with a dataflow language, designed to express parallelism. 2- Model your Architecture: PREESM simulates and generates code for a wide range of systems (e.g., ARM, DSP, FPGA). 3- Prototype and Run your Design: PREESM takes mapping decisions and provides early design space information such as scheduling, memory use, and core loads. PREESM and SPIDER are available on GitHub, and supported by tutorials and a reactive community. PREESM and SPIDER are part of the H2020 CERBERO toolchain. http://preesm.org

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UB06.6A RISC-V BASED VIRTUAL PROTOTYPE WITH AN INTEGRATED HARDWARE-IN-THE-LOOP RADAR
Authors:
Peer Adelt, Denis Zeinel, Bastian Koppelmann, Wolfgang Mueller and Christoph Scheytt, University of Paderborn, DE
Abstract
Our demonstration shows a small radar sensor in interactive communication with a RISC-V processor board and a RISC-V Virtual Prototype (VP) where the VP and the processor concurrently execute exactly the same target compiled software without a visible difference in reaction time. This demonstrates that widely available open source based virtual prototyping environments provide an adequate, stable, and efficient framework for the analysis of such embedded applications. The demonstration integrates our in-house developed 120GHz radar sensor via CAN bus with the SiFive RISC-V HiFive1 development board and our QEMU based VP. For the HiFive1 integration, we developed an Ardunio compliant board with an SPI-CAN adapter and a display. For the VP integration, we implemented the same components as QEMU QOM hardware models. Though the VP is executed in a linux based VirtualBox virtual machine on top of an additional host operating system, the impact of both is not visible in this setup.

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UB06.7SCCHARTS: THE KIELER SCCHARTS EDITOR - A MODULAR OPEN-SOURCE MODELING SUITE WITH AUTOMATIC DIAGRAM SYNTHESIS
Authors:
Steven Smyth1, Alexander Schulz-Rosengarten1, Christian Motika2 and Reinhard von Hanxleden1
1Kiel University, DE; 2Lufthansa Technik, DE
Abstract
When using high-level DSLs, the model-based approach promises a more transparent and efficient development process, for example in the hardware domain. By leveraging the compilation workflow to a meta level, the tool developer and the modeler can benefit from an interactive development process. Combined with modern transient view technologies, working with model transformation systems becomes transparent and less time consuming. Modeling tools should guide the modeler to potential issues and provide means to understand details about the transformations. The KIELER SCCharts Editor is a modular, open-source modeling suite, using the synchronous language SCCharts as main demonstrator. The editor supports compilation, automatic syntheses of intermediate results, and deployment to different platforms, both software and hardware. The modular concept of the compiler framework allows for rapid application and prototype development. The concepts can be applied to other languages or domains.

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UB06.8MASCARA: A MACHINE LEARNING AUTOMATIC SPEECH RECOGNITION PLATFORM FOR USERS WITH DYSARTHRIA
Authors:
Davide Mulfari, Gabriele Meoni, Marco Marini and Luca Fanucci, University of Pisa, IT
Abstract
We exploit machine learning technology to build Automatic Speech Recognition (ASR) solutions for people with dysarthria, a speech disorder characterized by low intelligibility of users' speaking and related to many motor disabilities. Within the field of ASR, nowadays popular voice assistant solutions (e.g.,Apple Siri) perform poorly on dysarthric speech processing, so users with disabilities cannot benefit from such technologies in many scenarios, like smart home. To address these issues, a custom ASR has been prototyped using a speaker dependent approach: it recognizes predefined keywords from disabled Italian persons who have already shared their voices. The demo shows our edge computing platform for speech recognition and its usage within the field of human computer interaction. We also present a mobile app allowing users to record and to share voice while they say selected keywords. With these data, we enrich our speech model in order to serve many application scenarios.

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UB06.9DESIGN SPACE EXPLORATION FRAMEWORKS FOR APPROXIMATE COMPUTING
Authors:
Alberto Bosio1, Olivier Sentieys2 and Daniel Ménard3
1University of Lyon, FR; 2University of Rennes, INRIA/IRISA, FR; 3INSA Rennes - IETR, FR
Abstract
Approximate Computing (AxC) investigates how to design energy efficient, faster, and less complex computing systems. Instead of performing exact computation and, consequently, requiring a high amount of resources, AxC aims to selectively relax the specifications, trading accuracy off for efficiency. The goal of this demonstrator, is to present a Design Space Exploration framework able to automatically explore the impact of different approximate operators on a given application accordingly to the required level of accuracy and the available HW architecture. The first demonstration relates to the word-length optimization of variables in a software or hardware system to explore cost (e.g., energy) and quality trade-off solution. The tool is scalable and targets both customized fixed-point and floating-point arithmetic. The second demonstration is about the use of other approximate techniques. The proposed demonstrator is linked with the DATE19 Monday tutorial M03.

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14:00End of session