UB05 Session 5

Printer-friendly version PDF version

Date: Wednesday, March 27, 2019
Time: 10:00 - 12:00
Location / Room:

LabelPresentation Title
Authors
UB05.1TIMING & POWER CHARACTERIZATION FRAMEWORK FOR EMBEDDED PROCESSORS
Authors:
Mark Kettner and Frank Oppenheimer, OFFIS - Institute for Information Technology, DE
Abstract
We present a framework that significantly reduces the effort for creating accurate energy/timing models for embedded processors covering different conditions (e.g. varying temperature and clock frequency). It supports the systematic collection of large amount of timing and power data needed to cover the complete microprocessors' ISA in different working conditions. Since manual measurements are tedious and error-prone we present an automated approach. The physical setup consists of a processor board, a power measurement device, a heating element and a logic analyser observing the processor's GPIOs. The software consists of a code-generator for characterization binaries, a control program which orchestrates the physical setup and the evaluation software which generates the desired timing and power data. We will demonstrate this framework for an ARM Cortex-M microcontroller and present interesting and even undocumented behaviour while using certain CPU and FPU features.

Download Paper (PDF)
UB05.2LOGIC MINIMIZER: LOGIC MINIMIZERS FOR PARTIALLY DEFINED FUNCTIONS
Authors:
Tsutomu Sasao, Kyu Matsuura, Kazuyuki Kai and Yukihiro Iguchi, Meiji University, JP
Abstract
Logic Minimizers for Partially Defined Functions Tsutomu Sasao, Meiji University, Kanagawa 214-0034, Japan. abstract: This demonstration shows a minimization system for partially defined functions. The minimizer reduces the number of the input variables to represent the function using linear transformations. Applications include implementations of random functions; code converter; IP address table; English word list; and URL list. Outline of Demonstration In the demonstration, a PC and a poster are used to show: * Introduction of partially defined functions. * A method to reduce variables by linear decompositions. * Implementation of code converters. * Implementation of IP address tables. * Implementation of English dictionaries. * Implementation of random functions. * Implementation of URL lists.

Download Paper (PDF)
UB05.3SWARM: SELF-ORGANIZED WIRING AND ARRANGEMENT OF RESPONSIVE MODULES
Authors:
Daniel Marolt and Jürgen Scheible, Hochschule Reutlingen, DE
Abstract
This demonstration exemplifies a new automation methodology for layout design of analog integrated circuits: Self-organized Wiring and Arrangement of Responsive Modules (SWARM). Based on the idea of decentralization, it addresses the task with an innovative multi-agent system. Its basic principle, similar to the roundup of a sheep herd, is to let responsive layout modules (implemented as procedural generators) interact with each other in a user-defined layout zone. Each module is allowed to autonomously move, rotate and deform itself, while a supervising control organ successively tightens the layout zone to steer the interaction towards increasingly compact layout arrangements. Considering various principles of self-organization, SWARM is able to evoke the phenomenon of emergence: although each module only has a limited viewpoint and selfishly pursues its personal objectives, remarkable overall solutions can emerge on the global scale.

Download Paper (PDF)
UB05.4HEPSYCODE-MC: ELECTRONIC SYSTEM-LEVEL METHODOLOGY FOR HW/SW CO-DESIGN OF MIXED-CRITICALITY EMBEDDED SYSTEMS
Authors:
Luigi Pomante1, Vittoriano Muttillo1, Marco Santic1 and Emilio Incerto2
1Università degli Studi dell'Aquila - DEWS, IT; 2IMT Lucca, IT
Abstract
Heterogeneous parallel architectures have been recently exploited for a wide range of embedded application domains. Embedded systems based on such kind of architectures can include different processor cores, memories, dedicated ICs and a set of connections among them. Moreover, especially in automotive and aerospace application domains, they are even more subjected to mixed-criticality constraints. So, this demo addresses the problem of the ESL HW/SW co-design of mixed-criticality embedded systems that exploit hypervisor (HPV) technologies. In particular, it shows an enhanced CSP/SystemC-based design space exploration step, in the context of an existing HW/SW co-design flow that, given the system specification is able to (semi)automatically propose to the designer: - a custom heterogeneous parallel HPV-based architecture; - an HW/SW partitioning of the application; - a mapping of the partitioned entities onto the proposed architecture.

Download Paper (PDF)
UB05.5CS: CRAZYSQUARE
Authors:
Federica Caruso1, Federica Caruso1, Tania Di Mascio1, Alessandro D'Errico1, Marco Pennese2, Luigi Pomante1, Claudia Rinaldi1 and Marco Santic1
1University of L'Aquila, IT; 2Ministry of Education, IT
Abstract
CrazySquare (CS) is an adaptive learning system, developed as a serious game for music education, specifically indicated for young teenager approaching music for the first time. CS is based on recent educative directions which consist of using a more direct approach to sound instead of the musical notation alone. It has been inspired by a paper-based procedure that is currently used in an Italian middle school. CS represents a support for such teachers who prefer involving their students in a playful dimension of learning rhythmic notation and pitch, and, at the same time, teaching playing a musical instrument. To reach such goals in a cost-effective way, CS fully exploits all the recent advances in the EDA domain. In fact, it is based on a framework composed of mobile applications that will be integrated with augmented reality HW/SW tools to provide virtual/augmented musical instruments. The proposed demo will show the main features of the current CS framework implementation.

Download Paper (PDF)
UB05.6MDC: MULTI-DATAFLOW COMPOSER TOOL: DATAFLOW TO HARDWARE COMPOSITION AND OPTIMIZATION OF RECONFIGURABLE ACCELERATORS
Authors:
Francesca Palumbo1, Carlo Sau2, Tiziana Fanni2, Claudio Rubattu1 and Luigi Raffo2
1University of Sassari, IT; 2University of Cagliari, IT
Abstract
UNICA-Eolab and UNISS-IDEA booth is demonstrating the capabilities of the Multi-Dataflow Component (MDC) tool: a model-based toolset for design and development of virtual coarse-grain reconfigurable (CGR) circuits. MDC provides multi-function substrate composition, optimization and integration in real environments. 1 Baseline Core: automatic composition of CGR substrates. Inputs kernels are provided as dataflow networks, and target agnostic RTL description is derived. [FPGA(1)/ASIC(2)] 2 Profiler: automated design space exploration to determine the optimal multi-functional CGR substrate given a set of constraints. [2] 3 Power Manager: power consumption minimization. Model level identification of the logic regions to determine optimal power/clock domains and apply saving strategies. [1/2] 4 Prototyper: automatic generation of Xilinx-compliant IPs and APIs. [1] MDC is part of the H2020 CERBERO toolchain. Material: http://sites.unica.it/rpct/ and IDEA Lab Channel www.goo.gl/7fXme3.

Download Paper (PDF)
UB05.7SCCHARTS: THE KIELER SCCHARTS EDITOR - A MODULAR OPEN-SOURCE MODELING SUITE WITH AUTOMATIC DIAGRAM SYNTHESIS
Authors:
Steven Smyth1, Alexander Schulz-Rosengarten1, Christian Motika2 and Reinhard von Hanxleden1
1Kiel University, DE; 2Lufthansa Technik, DE
Abstract
When using high-level DSLs, the model-based approach promises a more transparent and efficient development process, for example in the hardware domain. By leveraging the compilation workflow to a meta level, the tool developer and the modeler can benefit from an interactive development process. Combined with modern transient view technologies, working with model transformation systems becomes transparent and less time consuming. Modeling tools should guide the modeler to potential issues and provide means to understand details about the transformations. The KIELER SCCharts Editor is a modular, open-source modeling suite, using the synchronous language SCCharts as main demonstrator. The editor supports compilation, automatic syntheses of intermediate results, and deployment to different platforms, both software and hardware. The modular concept of the compiler framework allows for rapid application and prototype development. The concepts can be applied to other languages or domains.

Download Paper (PDF)
UB05.8LABSMILING: A SAAS FRAMEWORK, COMPOSED OF A NUMBER OF REMOTELY ACCESSIBLE TESTBEDS AND RELATED SW TOOLS, FOR ANALYSIS, DESIGN AND MANAGEMENT OF LOW DATA-RATE WIRELESS PERSONAL AREA NETWORKS BASED ON IEEE 802.15.4
Authors:
Carlo Centofanti, Luigi Pomante, Marco Santic and Walter Tiberti, University of L'Aquila, IT
Abstract
Low data-rate wireless personal area networks (LR-WPANs) are constantly increasing their presence in the fields of IoT, wearable, home automation, health monitoring. The development, deployment and testing of SW based on IEEE 802.15.4 standard (and derivations, e.g. 15.4e), require the exploitation of a testbed as the network grows in complexity and heterogeneity. This demo shows LabSmiling: a SaaS framework which connects testbeds deployed in a real-world-environment and the related SW tools that make available a meaningful (but still scalable) number of physical devices (sensor nodes) to developers. It provides a comfortable out-of-the-box service designed to fulfill developer needs giving them full control on single motes (program, reset, physical power on/off, up/down links, commands/messages/packets in/from the network). Advanced services are: full-customizable testing scenario, validation/testing protocol compliances/extensions, run low level packet sniffers with QoS metrics.

Download Paper (PDF)
UB05.9MECO: AN AUTONOMIC MANAGER FOR EDGE-COMPUTING PLATFORMS
Authors:
Gabriella D'Andrea, Tania Di Mascio, Luigi Pomante and Giacomo Valente, University of L'Aquila, IT
Abstract
In the Cyber-Physical-Systems word, the need for hardware platforms able to satisfy increasing requirements in computing performance, while keeping the adaptability imposed by the interactions with the physical world is leading on the use FPGAs, due to their inherent run-time reconfigurability. So, this demo presents an implementation of a self-adaptive loop for edge- computing devices targeting FPGAs. An adaptive run-time manager, together with a smart monitoring system, evaluates the quality of service and determines whether is convenient to perform a dynamic partial reconfiguration. The whole development flow, that exploits a library of elements to compose the monitoring system and then selects the appropriate manager, will be shown by means of a reference use case implemented on a Zynq Ultrascale+ SoC. Finally, a comparison among different functionalities will be illustrated as well.

Download Paper (PDF)
UB05.10RISC-V VP: RISC-V BASED VIRTUAL PROTOTYPE: AN OPEN SOURCE PLATFORM FOR MODELING AND VERIFICATION
Authors:
Vladimir Herdt1, Daniel Große2, Hoang M. Le1 and Rolf Drechsler2
1University of Bremen, DE; 2University of Bremen, DFKI GmbH, DE
Abstract
RISC-V, being an open and free Instruction Set Architecture (ISA), is gaining huge popularity as processor ISA in Internet-of-Things (IoT) devices. We propose an open source RISC-V based Virtual Prototype (VP) demonstrator (available at http://www.systemc-verification.org/riscv-vp). Our VP is implemented in standard compliant SystemC using a generic bus system with TLM 2.0 communication. At the heart of our VP is a 32 bit RISC-V (RV32IMAC) Instruction Set Simulator (ISS) with support for compressed instructions. This enables our VP to emulate IoT devices that work with a small amount of memory and limited resources. Our VP can be used as platform for early SW development and verification, as well as other system-level use cases. We support the GCC toolchain, provide SW debug, coverage measurement capabilities and support FreeRTOS. Our VP is designed as configurable and extensible platform. For example we provide the configuration for the RISC-V HiFive1 board from SiFive.

Download Paper (PDF)
12:00End of session