UB02 Session 2

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Date: Tuesday, March 26, 2019
Time: 12:30 - 15:00
Location / Room:

LabelPresentation Title
Authors
UB02.1TIMING & POWER CHARACTERIZATION FRAMEWORK FOR EMBEDDED PROCESSORS
Authors:
Mark Kettner and Frank Oppenheimer, OFFIS - Institute for Information Technology, DE
Abstract
We present a framework that significantly reduces the effort for creating accurate energy/timing models for embedded processors covering different conditions (e.g. varying temperature and clock frequency). It supports the systematic collection of large amount of timing and power data needed to cover the complete microprocessors' ISA in different working conditions. Since manual measurements are tedious and error-prone we present an automated approach. The physical setup consists of a processor board, a power measurement device, a heating element and a logic analyser observing the processor's GPIOs. The software consists of a code-generator for characterization binaries, a control program which orchestrates the physical setup and the evaluation software which generates the desired timing and power data. We will demonstrate this framework for an ARM Cortex-M microcontroller and present interesting and even undocumented behaviour while using certain CPU and FPU features.

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UB02.2WTG: WAVEFORM TRANSITION GRAPHS: A DESIGNER-FRIENDLY FORMALISM FOR ASYNCHRONOUS CIRCUITS
Author:
Danil Sokolov, Newcastle University, GB
Abstract
Asynchronous circuits are a promising class of digital circuits that has numerous advantages over their synchronous counterparts, especially in the domain of "little digital" speed-independent (SI) controllers. Nonetheless, their adoption has not been widespread, which in part is attributed to the difficulty of entry into complex models employed for specification of SI circuits, like Signal Transition Graphs (STGs), by electronic designers. We propose a new model called Waveform Transition Graphs (WTGs) which resembles the timing diagrams, that are very familiar to circuit designers, and defines its formal behaviour semantics. This formalization enables translation of the WTGs into equivalent STGs in order to reuse the existing body of research and tools for verification and logic synthesis of speed-independent circuits. The development of WTGs has been automated in the Workcraft toolkit (https://workcraft.org), allowing their conversion into STGs, verification and synthesis.

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UB02.3A FAST PROTOTYPING FRAMEWORK FOR SERVICE-ORIENTED AUTOMOTIVE APPLICATIONS
Authors:
Matthias Becker, Zhonghai Lu and De-Jiu Chen, KTH Royal Institute of Technology, SE
Abstract
Service-Oriented Architectures (SOA) provide a flexible platform for advanced automotive software applications. We present a research platform for fast prototyping of platform software and applications. The hardware is built around a RC car. Several sensors and actuators are connected over microcontrollers that can be accessed from higher-level ECUs over bus connections. User applications are executed on 4 Linux-based ECUs which communicate over a multi-hop Ethernet network. All communication of applications is realized over SOME-IP, an automotive middleware layer that is based on the SOA principle. The development framework generates code skeletons for user tasks, and all required management and configuration code of the underlying SOA framework, based on a user specified application model. It is then automatically transferred and compiled on the respective ECUs. We show the usability of the platform by a remote-operation scenario.

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UB02.4EQ-PYD-NET: ENERGY-EFFICIENT MONOCULAR DEPTH ESTIMATION ON ARM-BASED EMBEDDED PLATFORMS
Authors:
Andrea Calimera1, Valentino Peluso1, Antonio Cipolletta1, Matteo Poggi2, Fabio Tosi2 and Stefano Mattoccia2
1Politecnico di Torino, IT; 2Università di Bologna, IT
Abstract
The demonstration intends to show the implementation of energy-efficient monocular depth estimation using a low-cost CPU for low-power embedded systems. Through the demo we're going to present the PyD-Net depth estimation network, which consists of a lightweight CNN designed for CPUs and able to approach state-of-the-art accuracy. Then we introduce an accuracy-driven complexity reduction strategy based on a hardware-friendly fixed-point quantization. The objective is (i) to demonstrate the portability of the Quantized PyD-Net model into a general-purpose RISC architecture of the ARM Cortex family, (ii) quantify the accuracy-energy tradeoff of unsupervised monocular estimation to establish its use in the embedded domain. During the live demonstration the QPyD-Net will be made running on a Raspberry PI board powered by a Broadcom BCM2837 chip-set.

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UB02.5ACSIM: A NOVEL, SIMULATOR FOR HETEROGENEOUS PARALLEL AND DISTRIBUTED SYSTEMS THAT IN-CORPORATE CUSTOM HARDWARE ACCELERATORS
Authors:
Nikolaos Tampouratzis1 and Ioannis Papaefstathiou2
1Technical University of Crete, GR; 2Synelixis Solutions LTD, GR
Abstract
The growing use of hardware accelerators in both embedded (e.g. automotive) and high-end systems (e.g. Clouds) triggers an urgent demand for simulation frameworks that can simulate in an integrated manner all the components (i.e. CPUs, Memories, Networks, Hardware Accelerators) of a system-under-design (SuD). By utilizing such a simulator, software design can proceed in parallel with hardware development which results in the reduction of the so important time-to-market. The main problem, however, is that currently there is a shortage of such simulation frameworks; most simulators used for modelling the user applications (i.e. full-system CPU/Mem/Peripherals) lack any type of support for tailor-made hardware accelerators. ACSIM framework is the first known open-source, high-performance simulator that can handle holistically system-of-systems including processors, peripherals, accelerators and networks. The complete ACSIM framework together with its sophisticated GUI will be presented.

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UB02.6MASCARA: A MACHINE LEARNING AUTOMATIC SPEECH RECOGNITION PLATFORM FOR USERS WITH DYSARTHRIA
Authors:
Davide Mulfari, Gabriele Meoni, Marco Marini and Luca Fanucci, University of Pisa, IT
Abstract
We exploit machine learning technology to build Automatic Speech Recognition (ASR) solutions for people with dysarthria, a speech disorder characterized by low intelligibility of users' speaking and related to many motor disabilities. Within the field of ASR, nowadays popular voice assistant solutions (e.g.,Apple Siri) perform poorly on dysarthric speech processing, so users with disabilities cannot benefit from such technologies in many scenarios, like smart home. To address these issues, a custom ASR has been prototyped using a speaker dependent approach: it recognizes predefined keywords from disabled Italian persons who have already shared their voices. The demo shows our edge computing platform for speech recognition and its usage within the field of human computer interaction. We also present a mobile app allowing users to record and to share voice while they say selected keywords. With these data, we enrich our speech model in order to serve many application scenarios.

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UB02.7SCCHARTS: THE KIELER SCCHARTS EDITOR - A MODULAR OPEN-SOURCE MODELING SUITE WITH AUTOMATIC DIAGRAM SYNTHESIS
Authors:
Steven Smyth1, Alexander Schulz-Rosengarten1, Christian Motika2 and Reinhard von Hanxleden1
1Kiel University, DE; 2Lufthansa Technik, DE
Abstract
When using high-level DSLs, the model-based approach promises a more transparent and efficient development process, for example in the hardware domain. By leveraging the compilation workflow to a meta level, the tool developer and the modeler can benefit from an interactive development process. Combined with modern transient view technologies, working with model transformation systems becomes transparent and less time consuming. Modeling tools should guide the modeler to potential issues and provide means to understand details about the transformations. The KIELER SCCharts Editor is a modular, open-source modeling suite, using the synchronous language SCCharts as main demonstrator. The editor supports compilation, automatic syntheses of intermediate results, and deployment to different platforms, both software and hardware. The modular concept of the compiler framework allows for rapid application and prototype development. The concepts can be applied to other languages or domains.

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UB02.8RESCUE: EDA TOOLSET FOR INTERDEPENDENT ASPECTS OF RELIABILITY, SECURITY AND QUALITY IN NANOELECTRONIC SYSTEMS DESIGN
Authors:
Cemil Cem Gürsoy1, Guilherme Cardoso Medeiros2, Junchao Chen3, Nevin George4, Josie Esteban Rodriguez Condia5, Thomas Lange6, Aleksa Damljanovic5, Raphael Segabinazzi Ferreira4, Aneesh Balakrishnan6, Xinhui Anna Lai1, Shayesteh Masoumian7, Dmytro Petryk3, Troya Cagil Koylu2, Felipe Augusto da Silva8, Ahmet Cagri Bagbaba8 and Maksim Jenihhin1
1Tallinn University of Technology, EE; 2Delft University of Technology, NL; 3IHP, DE; 4BTU Cottbus-Senftenberg, DE; 5Politecnico di Torino, IT; 6IROC Technologies, FR; 7Intrinsic ID B.V., NL; 8Cadence Design Systems GmbH, DE
Abstract
The demonstrator will introduce an EDA toolset developed by a team of PhD students in the H2020-MSCA-ITN RESCUE project. The recent trends for the computing systems include machine intelligence in the era of IoT, complex safety-critical applications, extreme miniaturization of technologies and intensive interaction with the physical world. These trends set tough requirements on mutually dependent extra-functional design aspects. RESCUE is focused on the key challenges for reliability (functional safety, ageing, soft errors), security (tamper-resistance, PUF technology, intelligent security) and quality (novel fault models, functional test, FMEA/FMECA, verification/debug) and related EDA methodologies. The objective of the interdisciplinary cross-sectoral team from Tallinn UT, TU Delft, BTU Cottbus, POLITO, IHP, IROC, Intrinsic-ID, Cadence and Bosch is to develop in collaboration a holistic EDA toolset for modelling, assessment and enhancement of these extra-functional design aspects.

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UB02.9APODOSIS: ADVANCED ORCHESTRATOR FOR SMART-BUILDINGS
Authors:
Kostas Siozios1 and Stylianos Siskos2
1Aristotle University of Thessaloniki, GR; 2Department of Physics, Aristotle University of Thessaloniki, GR
Abstract
This work presents a distributed system for supporting advanced orchestrator of a smart grid environment. By efficiently control energy production from renewable sources and the energy loads, it is feasible to minimize the energy cost. In contrast to similar approaches, the proposed decision-making is performed in a distributed manner, while it also exhibits limited computational complexity.

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UB02.10A MODULAR RECONFIGURABLE DIGITAL MICROFLUIDICS PLATFORM
Authors:
Georgi Tanev1, Winnie Svendsen2 and Jan Madsen3
1Technical University of Denmark, DK; 2DTU Bioengineering, DK; 3DTU Compute, DK
Abstract
Digital microfluidics is a lab-on-a-chip (LOC) technology that allows for manipulation of a small amount of liquids on a chip-scaled device patterned with individually addressable electrodes. Microliter sized droplets can be programmatically dispensed, moved, mixed, react, split and stored thus implementing sample preparation protocols. Combining digital microfluidics with miniaturized analytical methods allows biomedical lab assays to be implemented on a LOC device that provides full sample-to-answer functionality. The growing complexity and integration of the LOC devices impose the need of software tools and hardware instruments to design, simulate, program and operate the broad range of LOC instrumentation needs. To address this matter, we present a modular reconfigurable microfluidics instrumentation platform (shown in Figure 1) capable of evolving to match the instrumentation needs of a specific LOC. The prototype shown in Figure 2 serves the purpose to demonstrate the platform.

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15:00End of session