UB01 Session 1

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Date: Tuesday, March 26, 2019
Time: 10:30 - 12:30
Location / Room:

LabelPresentation Title
Authors
UB01.1TIMING & POWER CHARACTERIZATION FRAMEWORK FOR EMBEDDED PROCESSORS
Authors:
Mark Kettner and Frank Oppenheimer, OFFIS - Institute for Information Technology, DE
Abstract
We present a framework that significantly reduces the effort for creating accurate energy/timing models for embedded processors covering different conditions (e.g. varying temperature and clock frequency). It supports the systematic collection of large amount of timing and power data needed to cover the complete microprocessors' ISA in different working conditions. Since manual measurements are tedious and error-prone we present an automated approach. The physical setup consists of a processor board, a power measurement device, a heating element and a logic analyser observing the processor's GPIOs. The software consists of a code-generator for characterization binaries, a control program which orchestrates the physical setup and the evaluation software which generates the desired timing and power data. We will demonstrate this framework for an ARM Cortex-M microcontroller and present interesting and even undocumented behaviour while using certain CPU and FPU features.

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UB01.2WTG: WAVEFORM TRANSITION GRAPHS: A DESIGNER-FRIENDLY FORMALISM FOR ASYNCHRONOUS CIRCUITS
Author:
Danil Sokolov, Newcastle University, GB
Abstract
Asynchronous circuits are a promising class of digital circuits that has numerous advantages over their synchronous counterparts, especially in the domain of "little digital" speed-independent (SI) controllers. Nonetheless, their adoption has not been widespread, which in part is attributed to the difficulty of entry into complex models employed for specification of SI circuits, like Signal Transition Graphs (STGs), by electronic designers. We propose a new model called Waveform Transition Graphs (WTGs) which resembles the timing diagrams, that are very familiar to circuit designers, and defines its formal behaviour semantics. This formalization enables translation of the WTGs into equivalent STGs in order to reuse the existing body of research and tools for verification and logic synthesis of speed-independent circuits. The development of WTGs has been automated in the Workcraft toolkit (https://workcraft.org), allowing their conversion into STGs, verification and synthesis.

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UB01.3MICROPLAN: MICRO-SYSTEM DESIGN AND PRODUCTION PLANNING TOOL
Authors:
Horst Tilman, Robert Fischbach and Jens Lienig, Technische Universität Dresden, DE
Abstract
We present a tool that enables to layout and plan the production of heterogeneous micro-systems. The tool consists of a simple layout editor, a visualization of the wafer utilization and eventually a calculation of the production cost for a given order quantity. Being superior with regard to performance, heterogeneous systems are often rendered unviable due to high production costs. However, using our tool allows users to design heterogeneous systems with an emphasis on low production costs. The tool is developed within the MICROPRINCE project and in close cooperation with X-Fab. The tool doesn't require installation and can be used by any visitor on their smartphone or computer.

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UB01.4HIPACC: SYNTHESIZING HIGH-PERFORMANCE IMAGE PROCESSING APPLICATIONS WITH HIPACC
Authors:
M. Akif Oezkan1, M. Akif Özkan,1, Oliver Reiche1, Bo Qiao1, Richard Membarth,2, Jürgen Teich1 and Frank Hannig1
1Friedrich–Alexander University Erlangen–Nürnberg (FAU), DE; 2German Research Center for Artificial Intelligence (DFKI), DE
Abstract
Programming heterogeneous platforms to achieve high performance is laborious since writing efficient code requires tuning at a low level with architecture-specific optimizations and is based on drastically differing programming models. Performance portability across different platforms can be achieved by decoupling the algorithm description from the target implementation. We present Hipacc (http://hipacc-lang.org), a framework consisting of an open-source image processing DSL and a compiler to target CPUs, GPUs, and FPGAs from the same program. We demonstrate Hipacc's productivity by considering real-world computer vision applications, e.g. optical flow, and generating target code (C++, OpenCL, C-based HLS) for three platforms (CPU and GPU in a laptop and an FPGA board). Finally, we showcase real-time processing of images acquired by a USB camera on these platforms.

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UB01.5ACSIM: A NOVEL, SIMULATOR FOR HETEROGENEOUS PARALLEL AND DISTRIBUTED SYSTEMS THAT IN-CORPORATE CUSTOM HARDWARE ACCELERATORS
Authors:
Nikolaos Tampouratzis1 and Ioannis Papaefstathiou2
1Technical University of Crete, GR; 2Synelixis Solutions LTD, GR
Abstract
The growing use of hardware accelerators in both embedded (e.g. automotive) and high-end systems (e.g. Clouds) triggers an urgent demand for simulation frameworks that can simulate in an integrated manner all the components (i.e. CPUs, Memories, Networks, Hardware Accelerators) of a system-under-design (SuD). By utilizing such a simulator, software design can proceed in parallel with hardware development which results in the reduction of the so important time-to-market. The main problem, however, is that currently there is a shortage of such simulation frameworks; most simulators used for modelling the user applications (i.e. full-system CPU/Mem/Peripherals) lack any type of support for tailor-made hardware accelerators. ACSIM framework is the first known open-source, high-performance simulator that can handle holistically system-of-systems including processors, peripherals, accelerators and networks. The complete ACSIM framework together with its sophisticated GUI will be presented.

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UB01.6MDC: MULTI-DATAFLOW COMPOSER TOOL: DATAFLOW TO HARDWARE COMPOSITION AND OPTIMIZATION OF RECONFIGURABLE ACCELERATORS
Authors:
Francesca Palumbo1, Carlo Sau2, Tiziana Fanni2, Claudio Rubattu1 and Luigi Raffo2
1University of Sassari, IT; 2University of Cagliari, IT
Abstract
UNICA-Eolab and UNISS-IDEA booth is demonstrating the capabilities of the Multi-Dataflow Component (MDC) tool: a model-based toolset for design and development of virtual coarse-grain reconfigurable (CGR) circuits. MDC provides multi-function substrate composition, optimization and integration in real environments. 1 Baseline Core: automatic composition of CGR substrates. Inputs kernels are provided as dataflow networks, and target agnostic RTL description is derived. [FPGA(1)/ASIC(2)] 2 Profiler: automated design space exploration to determine the optimal multi-functional CGR substrate given a set of constraints. [2] 3 Power Manager: power consumption minimization. Model level identification of the logic regions to determine optimal power/clock domains and apply saving strategies. [1/2] 4 Prototyper: automatic generation of Xilinx-compliant IPs and APIs. [1] MDC is part of the H2020 CERBERO toolchain. Material: http://sites.unica.it/rpct/ and IDEA Lab Channel www.goo.gl/7fXme3.

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UB01.7DESIGN SPACE EXPLORATION FRAMEWORKS FOR APPROXIMATE COMPUTING
Authors:
Alberto Bosio1, Olivier Sentieys2 and Daniel Ménard3
1University of Lyon, FR; 2University of Rennes, INRIA/IRISA, FR; 3INSA Rennes - IETR, FR
Abstract
Approximate Computing (AxC) investigates how to design energy efficient, faster, and less complex computing systems. Instead of performing exact computation and, consequently, requiring a high amount of resources, AxC aims to selectively relax the specifications, trading accuracy off for efficiency. The goal of this demonstrator, is to present a Design Space Exploration framework able to automatically explore the impact of different approximate operators on a given application accordingly to the required level of accuracy and the available HW architecture. The first demonstration relates to the word-length optimization of variables in a software or hardware system to explore cost (e.g., energy) and quality trade-off solution. The tool is scalable and targets both customized fixed-point and floating-point arithmetic. The second demonstration is about the use of other approximate techniques. The proposed demonstrator is linked with the DATE19 Monday tutorial M03.

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UB01.8RESCUE: EDA TOOLSET FOR INTERDEPENDENT ASPECTS OF RELIABILITY, SECURITY AND QUALITY IN NANOELECTRONIC SYSTEMS DESIGN
Authors:
Cemil Cem Gürsoy1, Guilherme Cardoso Medeiros2, Junchao Chen3, Nevin George4, Josie Esteban Rodriguez Condia5, Thomas Lange6, Aleksa Damljanovic5, Raphael Segabinazzi Ferreira4, Aneesh Balakrishnan6, Xinhui Anna Lai1, Shayesteh Masoumian7, Dmytro Petryk3, Troya Cagil Koylu2, Felipe Augusto da Silva8, Ahmet Cagri Bagbaba8 and Maksim Jenihhin1
1Tallinn University of Technology, EE; 2Delft University of Technology, NL; 3IHP, DE; 4BTU Cottbus-Senftenberg, DE; 5Politecnico di Torino, IT; 6IROC Technologies, FR; 7Intrinsic ID B.V., NL; 8Cadence Design Systems GmbH, DE
Abstract
The demonstrator will introduce an EDA toolset developed by a team of PhD students in the H2020-MSCA-ITN RESCUE project. The recent trends for the computing systems include machine intelligence in the era of IoT, complex safety-critical applications, extreme miniaturization of technologies and intensive interaction with the physical world. These trends set tough requirements on mutually dependent extra-functional design aspects. RESCUE is focused on the key challenges for reliability (functional safety, ageing, soft errors), security (tamper-resistance, PUF technology, intelligent security) and quality (novel fault models, functional test, FMEA/FMECA, verification/debug) and related EDA methodologies. The objective of the interdisciplinary cross-sectoral team from Tallinn UT, TU Delft, BTU Cottbus, POLITO, IHP, IROC, Intrinsic-ID, Cadence and Bosch is to develop in collaboration a holistic EDA toolset for modelling, assessment and enhancement of these extra-functional design aspects.

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UB01.9RISC-V VP: RISC-V BASED VIRTUAL PROTOTYPE: AN OPEN SOURCE PLATFORM FOR MODELING AND VERIFICATION
Authors:
Vladimir Herdt1, Daniel Große2, Hoang M. Le1 and Rolf Drechsler2
1University of Bremen, DE; 2University of Bremen, DFKI GmbH, DE
Abstract
RISC-V, being an open and free Instruction Set Architecture (ISA), is gaining huge popularity as processor ISA in Internet-of-Things (IoT) devices. We propose an open source RISC-V based Virtual Prototype (VP) demonstrator (available at http://www.systemc-verification.org/riscv-vp). Our VP is implemented in standard compliant SystemC using a generic bus system with TLM 2.0 communication. At the heart of our VP is a 32 bit RISC-V (RV32IMAC) Instruction Set Simulator (ISS) with support for compressed instructions. This enables our VP to emulate IoT devices that work with a small amount of memory and limited resources. Our VP can be used as platform for early SW development and verification, as well as other system-level use cases. We support the GCC toolchain, provide SW debug, coverage measurement capabilities and support FreeRTOS. Our VP is designed as configurable and extensible platform. For example we provide the configuration for the RISC-V HiFive1 board from SiFive.

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UB01.10SETA-RAY: A NEW IDE TOOL FOR PREDICTING, ANALYZING AND MITIGATING RADIATION-INDUCED SOFT ERRORS ON FPGAS
Authors:
Luca Sterpone, Boyang Du and Sarah Azimi, Politecnico di Torino, IT
Abstract
One of the main concern for FPGA adopted in mission critical application such as space and avionic fields is radiation-induced soft errors. Therefore, we propose an IDE including two software tools compatible with commercial EDA tools. RAD-RAY as the first and only developed tool capable to predict the source of the SET phenomena by taking in to account the features of the radiation environment such as the type, LET and interaction angle of the particles, the material and physical layout of the device exposed to the radiation. The predicted source SET pulse in provided to the SETA tool as the second developed tool integrated with the commercial FPGA design tool for evaluating the sensitivity of the industrial circuit implemented on Flash-based FPGA and mitigate the original netlist based on the performed analysis. This IDE is supported by ESA and Thales Alenia Space. It has been applied to the EUCLID space mission project that will be launched in 2021.

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12:30End of session