9.6 Reliability of highly-parallel architectures: an industrial perspective

Printer-friendly version PDF version

Date: Thursday, March 28, 2019
Time: 08:30 - 10:00
Location / Room: Room 6

Chair:
Doris Keitel-Schulz, Infineon Technologies, DE, Contact Doris Keitel-Schulz

Co-Chair:
Fabien Clermidy, CEA, FR, Contact Fabien Clermidy

This session addresses the issues of proving, verifying and enhancing highly-parallel designs on four different application domains ranging from Solid-State-Drive to 5G

TimeLabelPresentation Title
Authors
08:309.6.1AURIX TC277 MULTICORE CONTENTION MODEL INTEGRATION FOR AUTOMOTIVE APPLICATIONS
Speaker:
Jaume Abella, Barcelona Supercomputing Center (BSC), ES
Authors:
Enrico Mezzetti1, Luca Barbina2, Jaume Abella3, Stefania Botta2 and Francisco Cazorla4
1Barcelona Supercomputing Center (BSC), ES; 2Magneti Marelli S.p.A., IT; 3Barcelona Supercomputing Center (BSC-CNS), ES; 4Barcelona Supercomputing Center and IIIA-CSIC, ES
Abstract
Embedded systems industry needs reliable and tight worst-case execution time (WCET) estimates for critical applications running on multicores, as a prerequisite to their adoption. While industry already uses reliable tools for single-core WCET estimation and several multicore contention models (MCMs) have been proposed, their combination have not been shown to be fully compatible with the automotive industrial practice yet. This paper reduces this gap by presenting a framework for the integration of MCMs into industrial WCET estimation practice. We illustrate such integration for a Magneti Marelli powertrain control unit on an Infineon AURIX TC277 multicore platform.
09:009.6.2SEAMLESS SOC VERIFICATION USING VIRTUAL PLATFORMS: AN INDUSTRIAL CASE STUDY
Speaker:
Kyungsu Kang, Samsung Electronics, KR
Authors:
Kyungsu Kang, Sangho Park, Byeongwook Bae, Jungyun Choi, SungGil Lee, Byunghoon Lee and Jong-Bae Lee, Samsung, KR
Abstract
As SoC (System-on-Chip) complexity continues to increase, function/performance verification is required in the middle of design process (before tape-out) to reduce the possible risks ranging from over-design to non-compliance with the design specifications. In this paper, we propose a seamless SoC verification. The proposed methodology exploits a modern virtual platform (VP) technology which can combine high-level C++ firmware, timing-accurate SystemC models, and RTL (register-transfer level) designs. Thus, the full-chip level verification can be done at any design stages in the whole development process. With experimental results, this paper shows the benefits and lessons of using VPs.
09:309.6.3MULTICORE EARLY DESIGN STAGE GUARANTEED PERFORMANCE ESTIMATES FOR THE SPACE DOMAIN
Speaker:
Mikel Fernandez, Barcelona Supercomputing Center, ES
Authors:
Mikel Fernandez1, Gabriel Fernandez1, Jaume Abella2 and Francisco Cazorla3
1Barcelona Supercomputing Center, ES; 2Barcelona Supercomputing Center (BSC-CNS), ES; 3Barcelona Supercomputing Center and IIIA-CSIC, ES
Abstract
The ability to produce early guaranteed performance (worst-case execution time) estimations for multicores, i.e. before software from different providers gets integrated onto the same critical system, is pivotal. This helps reducing lately-detected costly-to-handle timing violations. An existing methodology creates 'copy' (surrogate) applications from the execution in isolation of each target application. Surrogate applications can be used to upperbound multicore contention delay, and hence WCET estimates in multicores. However, this methodology has only been shown to work on a simulation environment. In this paper we show the work we have done to adapt this technology to a real multicore processor for the space domain.
09:459.6.4POLAR CODE DECODER FRAMEWORK
Speaker:
Timo Lehnigk-Emden, Creonic GmbH, DE
Authors:
Timo Lehnigk-Emden1, Matthias Alles1, Claus Kestel2 and Norbert Wehn2
1Creonic GmbH, DE; 2University of Kaiserslautern, DE
Abstract
Polar codes gained large interest in the last years since they are the first channel codes that are proven to achieve channel capacity. Due to this property, Polar codes were recently adopted for the 5G standard. We present an industrial framework for the generation of Polar code decoders for highest data throughput. The framework automatically generates VHDL models ready for synthesis, placement and routing and corresponding simulation models to assess the communications performance. This framework enables Polar code decoder IP providers to give fast feedback to customers on communications and implementation performance. We demonstrate that this framework outperforms existing manually optimized decoders especially in terms of energy efficiency.
10:00End of session
Coffee Break in Exhibition Area



Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Lunch Breaks (Lunch Area)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 26, 2019

Wednesday, March 27, 2019

Thursday, March 28, 2019