7.4 Low Power Design: From Highly-Optimized Power Delivery Networks to CNN Accelerators

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Date: Wednesday, March 27, 2019
Time: 14:30 - 16:00
Location / Room: Room 4

Chair:
Pascal Vivet, CEA-Leti, FR, Contact Pascal Vivet

Co-Chair:
Andrea Bartolini, Università di Bologna, IT, Contact Andrea Bartolini

The session presents four papers covering power optimization through the whole design stack. The first paper presents an innovative power mesh IR optimization in an advanced technology node. The second paper presents a new formulation and optimization strategy to get the best efficiency from on-chip switch cap converters for heterogeneous many cores. While the third paper presents an optimized power delivery network for 3D integrated systems. Finally, the fourth paper presents a power efficient accelerator based on associative CAMs for CNN inference.

TimeLabelPresentation Title
Authors
14:307.4.1DETAILED PLACEMENT FOR IR DROP MITIGATION BY POWER STAPLE INSERTION IN SUB-10NM VLSI
Speaker:
Minsoo Kim, UC San Diego, US
Authors:
Sun ik Heo1, Andrew Kahng2, Minsoo Kim3, Lutong Wang3 and Chutong Yang3
1Samsung Electronics Co., Ltd.,, KR; 2UCSD, US; 3UC San Diego, US
Abstract
Power Delivery Network (PDN) is one of the most challenging topics in modern VLSI design. Due to aggressive technology node scaling, resistance of back-end-of-line (BEOL) layers increases dramatically in sub-10nm VLSI, causing high supply voltage (IR) drop. To solve this problem, pre-placed or post-placed power staples are inserted in pin-access layers to connect adjacent power rails and reduce PDN resistance, at the cost of reduced routing flexibility, or reduced power staple insertion opportunity. In this work, we propose dynamic programming-based single-row and double-row detailed placement optimizations to maximize the power staple insertion in a post-placement flow. We further propose metaheuristics to improve the quality of result. Compared to the traditional post-placement flow, we achieve up to 13.2% (10mV) reduction in IR drop, with almost no WNS degradation.
15:007.4.2OPTIMIZING THE ENERGY EFFICIENCY OF POWER SUPPLY IN HETEROGENEOUS MULTICORE CHIPS WITH INTEGRATED SWITCHED-CAPACITOR CONVERTERS
Speaker:
Lu Wang, ShanghaiTech University, CN
Authors:
Lu Wang1, Leilei Wang1, Dejia Shang1, Cheng Zhuo2 and Pingqiang Zhou1
1ShanghaiTech University, CN; 2Zhejiang University, CN
Abstract
Energy efficiency is a major concern in heterogeneous multi-core chips. Due to the switching-capacitor converter (SCC) has wide output voltages and high potential ratio efficiency, they are widely used in multi-core chips. In this paper we propose the optimization of Metal-Insulator-Metal (MIM) capacitance resource allocation and converter ratio selection for SCCs to improve the power efficiency by transforming the mixed integer nonlinear programming (MINLP) problems into a series of convex problems. The experimental results show that our approach can achieve a 9%-13% improvement in power efficiency and can be applied to more complicated heterogeneous multicore scenarios.
15:307.4.3POWER DELIVERY PATHFINDING FOR EMERGING DIE-TO-WAFER INTEGRATION TECHNOLOGY
Speaker:
Seungwon Kim, Ulsan National Institute of Science and Technology, KR
Authors:
Andrew B. Kahng1, Seokhyeong Kang2, Seungwon Kim3, Kambiz Samadi4 and Bangqi Xu1
1UC San Diego, US; 2Pohang University of Science and Technology, KR; 3Ulsan National Institute of Science and Technology (UNIST), KR; 4Qualcomm Technologies, Inc.,
Abstract
In advanced technology nodes, emerging die-towafer (D2W) integration technology is a promising "More Than Moore" lever for continued scaling of system capability and value. In D2W 3D IC implementation, the power delivery network (PDN) is crucial to meeting design specifications. However, determining the optimal PDN design is nontrivial. On the one hand, to meet the IR drop requirement, denser power mesh is desired. On the other hand, to meet the timing requirement for a high-utilization design, more routing resource should be available for signal routing. Moreover, additional competition between signal routing and power routing is caused by intertier vertical interconnects in 3D IC. In this paper, we propose a power delivery pathfinding methodology for emerging die-towafer integration, which seeks to identify an optimal or nearoptimal PDN for a given design and PDN specification. Our pathfinding methodology exploits models for routability and worst IR drop, which helps reduce iterations between PDN design and circuit design in 3D IC implementation. We present validations with real design examples and a 28nm foundry technology.
15:457.4.4ENERGY-EFFICIENT CONVOLUTIONAL NEURAL NETWORKS VIA RECURRENT DATA REUSE
Speaker:
Luca Mocerino, Politecnico di Torino, IT
Authors:
Luca Mocerino, Valerio Tenace and Andrea Calimera, Politecnico di Torino, IT
Abstract
Deep learning (DL) algorithms have substantially improved in terms of accuracy and efficiency. Convolutional Neural Networks (CNNs) are now able to outperform traditional algorithms in computer vision tasks such as object classification, detection, recognition, and image segmentation. They represent an attractive solution for many embedded applications which may take advantage from machine-learning at the edge. Needless to say, the key to success lies under the availability of efficient hardware implementations which meet the stringent design constraints. Inspired by the way human brains process information, this paper presents a method that improves the processing efficiency of CNNs leveraging their repetitiveness. More specifically, we introduce (i) a clustering methodology that maximizes weights/activation reuse, and (ii) the design of a heterogeneous processing element which integrates a Floating-Point Unit (FPU) with an associative memory that manages recurrent patterns. The experimental analysis reveals that the proposed method achieves substantial energy savings with low accuracy loss, thus providing a practical design option that might find application in the growing segment of edge-computing.
16:00IP3-17, 717ADAPTIVE WORD REORDERING FOR LOW-POWER INTER-CHIP COMMUNICATION
Speaker:
Eleni Maragkoudaki, University of Manchester, GB
Authors:
Eleni Maragkoudaki1, Przemyslaw Mroszczyk2 and Vasilis Pavlidis1
1University of Manchester, GB; 2Qualcomm, IE
Abstract
The energy for data transfer has an increasing effect on the total system energy as technology scales, often overtaking computation energy. To reduce the power of inter-chip interconnects, an adaptive encoding scheme called Adaptive Word Reordering (AWR) is proposed that effectively decreases the number of signal transitions, leading to a significant power reduction. AWR outperforms other adaptive encoding schemes in terms of decrease in transitions, yielding up to 73% reduction in switching. Furthermore, complex bit transition computations are represented as delays in the time domain to limit the power overhead due to encoding. The saved power outweighs the overhead beyond a moderate wire length where the I/O voltage is assumed equal to the core voltage. For a typical I/O voltage, the decrease in power is significant reaching 23% at just 1 mm.
16:00End of session
Coffee Break in Exhibition Area



Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Lunch Breaks (Lunch Area)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the ""Lunch Area"" to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 26, 2019

  • Coffee Break 10:30 - 11:30
  • Lunch Break 13:00 - 14:30
  • Awards Presentation and Keynote Lecture in ""TBD"" 13:50 - 14:20
  • Coffee Break 16:00 - 17:00

Wednesday, March 27, 2019

  • Coffee Break 10:00 - 11:00
  • Lunch Break 12:30 - 14:30
  • Awards Presentation and Keynote Lecture in ""TBD"" 13:30 - 14:20
  • Coffee Break 16:00 - 17:00

Thursday, March 28, 2019

  • Coffee Break 10:00 - 11:00
  • Lunch Break 12:30 - 14:00
  • Keynote Lecture in ""TBD"" 13:20 - 13:50
  • Coffee Break 15:30 - 16:00