7.1 Special Day on "Embedded Meets Hyperscale and HPC" Session: Tools and Runtime Systems

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Date: Wednesday, March 27, 2019
Time: 14:30 - 16:00
Location / Room: Room 1

Chair:
Christian Plessl, Paderborn University, DE, Contact Christian Plessl

Co-Chair:
Christoph Hagleitner, IBM Research, CH, Contact Christoph Hagleitner

Programming and operating heterogeneous computing systems that use multiple computing resources poses additional challenges to the programmer, e.g. handling different programming and execution models, partitioning application to exploit the strength of each resource type, or modeling and optimizing the overall and efficiency. In this session, we will discuss tools and runtime systems that support the developer with these tasks by raising the level of abstraction for application specification

TimeLabelPresentation Title
Authors
14:307.1.1GRAPH-BASED HARDWARE REPRESENTATION FOR RAPID AND PRECISE PERFORMANCE MODELING
Speaker:
Jeffrey S Vetter, Oak Ridge National Laboratory, US
Authors:
Mehmet E Belviranli and Jeffrey S Vetter, Oak Ridge National Laboratory, US
Abstract
The slowdown of Moore's law has caused an escalation in architectural diversity over the last decade and agile development of domain-specific heterogeneous chips is becoming a high priority. However, this agile development must also consider portable programming environments and other architectural constraints into the system design. More importantly, understanding the role of each component in an end-to-end system design is important to both architects and application developers, and must include metrics like power, performance, space, cost, and reliability. Being able to quickly and precisely characterize the needs of an application in the early stages of hardware design is an essential step towards converging on primary components of these increasingly heterogeneous platforms. In this paper, we introduce FLAME, a graph-based machine representation to flexibly model a given hardware design at any desired resolution while providing the ability to refine specific components along the hierarchy. FLAME allows each processing unit in the system to declare their specific capabilities and enables higher level elements to reuse and leverage these declarations to form more complex system topologies. Applications are characterized with the Aspen application model; each component has the ability to report their characteristic behavior for a given application model against a supported metric. We demonstrate the feasibility of FLAME for several workloads via multi-core machine representations on different levels abstraction.
15:007.1.2HOMOGENIZING HETEROGENEITY: THE OMPSS APPROACH
Author:
Jesus Labarta, Barcelona Supercomputing Center, ES
Abstract
Initially aiming at the node level parallelization of HPC science and engineering codes, OmpSs has been proposing programming model features to enable the incremental migration of applications to the recent and foreseeable architectures. Heterogeneity is and will be an important characteristic of such systems but the spectrum of future devices is wide and open. In this context, ensuring programmer productivity and quality of life as well as code portability requires mechanisms that make heterogeneous systems appear as uniform as possible. The OmpSs task based approach provides such homogenization of heterogeneity, enabling the execution of a single program on nodes with just multicores or including GPUs or FPGAs.
15:307.1.3AUTOMATIC CODE RESTRUCTURING FOR FPGAS: CURRENT STATUS, TRENDS AND OPEN ISSUES
Author:
João M. P. Cardoso, University of Porto/FEUP, PT
Abstract
The customization features, large scale parallel computing power, heterogeneity, and hardware reconfigurability of FPGAs make them suitable computing platforms in many application domains, from high-performance to embedded computing. FPGAs are not only able to provide hardware acceleration to algorithms but to also provide complete system solutions with low cost and efficient performance/energy tradeoffs. In recent years we witnessed significant maturity levels in high-level synthesis (HLS) and in FPGA design flows, helping the mapping of computations to FPGAs. However, in order that HLS tools are able to achieve efficient FPGA implementations, applications source code typically needs substantial code restructuring/refactoring. This is neither a simple task for software developers nor for compilers and its automation has become an important line of research. This presentation will start by motivating the investment on source-to-source compilers and then will focus on some of the problems regarding automatic code restructuring. We will focus on the automatic code restructuring improvements over the last years, the trends, the challenges, and on the aspects that make automatic code restructuring an exciting research subject. Finally, we will show our recent and promising approach to automatic code restructuring.
16:00End of session
Coffee Break in Exhibition Area



Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Lunch Breaks (Lunch Area)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the ""Lunch Area"" to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 26, 2019

  • Coffee Break 10:30 - 11:30
  • Lunch Break 13:00 - 14:30
  • Awards Presentation and Keynote Lecture in ""TBD"" 13:50 - 14:20
  • Coffee Break 16:00 - 17:00

Wednesday, March 27, 2019

  • Coffee Break 10:00 - 11:00
  • Lunch Break 12:30 - 14:30
  • Awards Presentation and Keynote Lecture in ""TBD"" 13:30 - 14:20
  • Coffee Break 16:00 - 17:00

Thursday, March 28, 2019

  • Coffee Break 10:00 - 11:00
  • Lunch Break 12:30 - 14:00
  • Keynote Lecture in ""TBD"" 13:20 - 13:50
  • Coffee Break 15:30 - 16:00