5.3 EU Projects

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Date: Wednesday, March 27, 2019
Time: 08:30 - 10:00
Location / Room: Room 3

Chair:
Martin Schoeberl, Technical University of Denmark, DK, Contact Martin Schöberl

EU Projects

TimeLabelPresentation Title
Authors
08:305.3.1AXIOM: A SCALABLE, EFFICIENT AND RECONFIGURABLE EMBEDDED PLATFORM
Speaker:
Roberto Giorgi, University of Siena, IT
Authors:
Roberto Giorgi, Marco Procaccini and Farnam Khalili, University of Siena, IT
Abstract
Cyber-Physical Systems (CPSs) are becoming widely used in every application that requires interaction between humans and the physical environment. People expect this interaction to happen in real-time and this creates pressure onto system designs due to the ever-higher demand for data processing in the shortest possible and predictable time. Additionally, easy programmability, energy efficiency, and modular scalability are also important to ensure these systems to become widespread. All these requirements push new scientific and technological challenges towards the engineering community. The AXIOM project (Agile, eXtensible, fast I/O Module), presented in this paper, introduces a new hardware-software platform for CPS, which can provide an easy parallel programming model and fast connectivity, in order to scale-up performance by adding multiple boards. The AXIOM platform consists of a custom board based on a Xilinx Zynq Ultrascale+ ZU9EG SoC including four 64-bit ARM cores, the Arduino socket and four high-speed (up to 18~Gbps) connectors on USB-C receptacles. By relying on this hardware, DF-Threads, a novel execution model based on dataflow modality, has been developed and tested. In this paper, we highlight some major conclusions of the AXIOM project, such as the gain in performance compared to other parallel programming models such as OpenMPI and Cilk.
09:005.3.2APPLICATIONS OF COMPUTATION-IN-MEMORY ARCHITECTURES BASED ON MEMRISTIVE DEVICES
Speaker:
Said Hamdioui, Delft University of Technology, NL
Authors:
Said Hamdioui1, Abu Sebastian2, Shidhartha Das3, Geethan Karunaratne4, Hoang Anh Du Nguyen1, Manuel Le Gallo2, Siebren Schaafsma5, Abbas Rahimi4, Mottaqiallah Taouil6, Francky Catthoor7, Luca Benini4, Sandeep Pande5 and Fernando G. Redondo8
1Delft University of Technology, NL; 2IBM, CH; 3ARM Ltd., GB; 4ETHZ, CH; 5IMEC, NL; 6TUDelft, NL; 7IMEC, BE; 8ARM, GB
Abstract
Today's computing architectures and device technologies are unable to meet the increasingly stringent demands on energy and performance posed by emerging applications. Therefore, alternative computing architectures are being explored that leverage novel post-CMOS device technologies. One of these is a Computation-in-Memory architecture based on memristive devices. This paper describes the concept of such an architecture and shows different applications that could significantly benefit from it. For each application, the algorithm, the architecture, the primitive operations, and the potential benefits are presented. The applications cover the domains of data analytics, signal processing, and machine learning.
09:155.3.3CHIP-TO-CLOUD: AN AUTONOMOUS AND ENERGY EFFICIENT PLATFORM FOR SMART VISION APPLICATIONS
Speaker:
Simone Ciccia, Istituto Superiore Mario Boella (ISMB), IT
Authors:
Alberto Scionti, Simone Ciccia, Olivier Terzo and Giorgio Giordanengo, Istituto Superiore Mario Boella, IT
Abstract
Modern Cloud architectures encompass computing and communication elements that span from traditional data center computing nodes (offering almost infinite resources to satisfy any application demands) to edge-computing and IoT devices (to sense and act on the real world). This paper presents the Cloud architecture devised within the OPERA project, which provides new levels of energy efficiency as a full chip-to-Cloud solution. Focusing on a smart vision application (i.e., road traffic monitoring), the paper presents novel architectural solutions optimised to achieve high energy efficiency at any level: i) the computing elements supporting the acceleration of State-of-the-Art CNNs; and ii) an innovative wireless communication subsystem. Unlike conventional designs, our wireless communication subsystem exploits the advantages of software defined radio (SDN) firmware to control a reconfigurable antenna. To further extend the application range, an energy harvesting module is used to supply power. Besides the edge-IoT, high-density accelerated servers offer capabilities of running complex algorithms within a small power envelop. The effectiveness of the whole architecture has been tested in a real context (i.e., 2 installation sites). In-field measurements demonstrate our claim: high-performance coupled with high energy efficiency over the whole system.
09:305.3.4ON THE USE OF HACKATHONS TO ENHANCE COLLABORATION IN LARGE COLLABORATIVE PROJECTS -A PRELIMINARY CASE STUDY OF THE MEGAM@RT2 EU PROJECT -
Speaker:
Gunnar Widforss, Mälardalen University, SE
Authors:
Andrey Sadovykh1, Dragos Truscan2, Pierluigi Pierini3, Gunnar Widforss4, Adnan Ashraf2, Hugo Bruneliere5, Pavel Smrz6, Alessandra Bagnato7, Wasif Afzal4 and Alexandra Espinosa Hortelano4
1SOFTEAM; Innopolis University, FR; 2ABO AKADEMI, FI; 3Intecs S.p.A., IT; 4MAELARDALENS HOEGSKOLA, SE; 5ASSOCIATION POUR LA RECHERCHE ET LE DEVELOPPEMENT DES METHODES ET PROCESS, FR; 6Brno University of Technology, CZ; 7SOFTEAM, FR
Abstract
In this paper, we present the MegaM@Rt2 ECSEL project and discuss our approach for fostering collaboration in the project. We choose an "internal hackathon" approach that focuses on technical collaboration between case study owners and tool/method providers. The novelty of the approach is that we organize the technical workshop as a challenge-based contest at our regular project progress meetings participated by all partners in the project. Case study partners submit their challenges related to the project goals and their use cases in advance. These challenges are concise enough to be experimented within approximately 4 hours. Teams are then formed to address those challenges. The teams comprise of tool/method providers, case study owners and researchers/developers from other consortium members. On the "hackathon" day, partners work together to come with results addressing the challenges that are both interesting to encourage collaboration and convincing to continue further deeper investigations. Obtained results demonstrate that the "hackathon" approach stimulated knowledge exchanges among project partners and triggered new collaborations, notably between tool providers and use case owners.
09:455.3.5REALIZATION OF FOUR-TERMINAL SWITCHING LATTICES: TECHNOLOGY DEVELOPMENT AND CIRCUIT MODELING
Speaker:
Mustafa Altun, Istanbul Technical University, TR
Authors:
Serzat Safaltin1, Oguz Gencer1, M. Ceylan Morgul1, Levent Aksoy1, Sebahattin Gurmen1, Csaba Andras Moritz2 and Mustafa Altun1
1Istanbul Technical University, TR; 2University of Massachusetts, Amherst, US
Abstract
Our European Union's Horizon-2020 project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Within the project, we investigate different computing models based on either two-terminal switches, realized with field effect transistors, resistive and diode devices, or four-terminal switches. Although a four-terminal switch based model offers a significant area advantage, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. In this study, we answer these questions. First, by using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. For this purpose, we try different semiconductor gate materials in different formations of geometric shapes. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch. Finally, we successfully perform Spice circuit simulations on four-terminal switches with different sizes. As a follow-up work within the project, we will proceed to the fabrication step.
10:00IP2-11, 1031CO-DESIGN IMPLICATIONS OF ON-DEMAND-ACCELERATION FOR CLOUD HEALTHCARE ANALYTICS: THE AEGLE APPROACH
Speaker:
Konstantina Koliogeorgi, National Technical University of Athens, GR
Authors:
Dimosthenis Masouros1, Konstantina Koliogeorgi1, Georgios Zervakis2, Alexandra Kosvyra3, Achilleas Chytas3, Sotirios Xydis1, Ioanna Chouvarda3 and Dimitrios Soudris4
1National Technical University of Athens, GR; 2National Technical University of Athens (NTUA), GR; 3Aristotle University of Thessaloniki, GR; 4NTUA, GR
Abstract
Nowadays, big data and machine learning are transforming the way we realize and manage our data. Even though the healthcare domain has recognized big data analytics as a prominent candidate, it has not yet fully grasped their promising benefits that allow medical information to be converted to useful knowledge. In this paper, we introduce AEGLE's big data infrastructure provided as a Platform as a Service. Utilizing the suite of genomic analytics from the Chronic Lymphocytic Leukaemia (CLL) use case, we show that on-demand acceleration is profitable w.r.t a pure software cloud-based solution. However, we further show that on-demand acceleration is not offered as a "free-lunch" and we provide an in-depth analysis and lessons learnt on the co-design implications to be carefully considered for enabling cost-effective acceleration at the cloud-level.
10:01IP2-12, 1045MODULAR FPGA ACCELERATION OF DATA ANALYTICS IN HETEROGENOUS COMPUTING
Authors:
Christoforos Kachris1, Dimitrios Soudris2 and Elias Koromilas2
1National Technical University of Athens, GR; 2NTUA, GR
Abstract
Emerging cloud applications like machine learning, AI and big data analytics required high performance computing systems that can sustain the increased amount of data processing without consuming excessive power. Towards this end, many cloud operators have started deploying hardware accelerators, like FPGAs, to increase the performance of computational intensive tasks but increasing the programming complexity to utilize these accelerators. VINEYARD has developed an efficient framework that allows the seamless deployment and utilization of hardware accelerators in the cloud without increasing the programming complexity and offering the flexibility of software packages. This paper presents a modular approach for the development of hardware IP blocks that are used for the acceleration of data analytics. The modular approach allows the automatic development of integrated hardware designs for the acceleration of data analytics. The proposed framework shows the data analytics modules can be used to achieve up to 10x speedup compared to high performance general-purpose processors.
10:00End of session
Coffee Break in Exhibition Area



Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Lunch Breaks (Lunch Area)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the ""Lunch Area"" to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 26, 2019

  • Coffee Break 10:30 - 11:30
  • Lunch Break 13:00 - 14:30
  • Awards Presentation and Keynote Lecture in ""TBD"" 13:50 - 14:20
  • Coffee Break 16:00 - 17:00

Wednesday, March 27, 2019

  • Coffee Break 10:00 - 11:00
  • Lunch Break 12:30 - 14:30
  • Awards Presentation and Keynote Lecture in ""TBD"" 13:30 - 14:20
  • Coffee Break 16:00 - 17:00

Thursday, March 28, 2019

  • Coffee Break 10:00 - 11:00
  • Lunch Break 12:30 - 14:00
  • Keynote Lecture in ""TBD"" 13:20 - 13:50
  • Coffee Break 15:30 - 16:00