4.8 Embedded Tutorial: Paving the Way for Very Large Scale Integration of Superconductive Electronics

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Date: Tuesday, March 26, 2019
Time: 17:00 - 18:30
Location / Room: Exh. Theatre

Organisers:
Jamil Kawa, Synopsys, US, Contact Jamil Kawa
Massoud Pedram, USC, US, Contact massoud pedram

Chair:
Jamil Kawa, Synopsys, US, Contact Jamil Kawa

Superconductive electronics (SCE) based on single flux quantum (SFQ) family of logic cells has appeared as a potent and within-reach "beyond-CMOS" technology. With proven switching speeds in 100's of GHz and energy dissipation approaching 10^(-19) Joules per transition (and lower for the adiabatic family), it is one of the most promising post-CMOS technologies that can break the current performance limit of 4 or so GHz CMOS processors, delivering a 30GHz single-threaded performance for a SCE processor. The state-of-the-art in terms of libraries, simulation and analysis, compact modeling, synthesis, physical design of SFQ-based logic is far behind that of CMOS, with semi-manual design of 16-bit SFQ adders, simple filters and ADCs, and bit-serial processors defining the state-of-the-art. To fulfill the potential of SCE logic families, it is essential that design methodologies and tools are developed to enable fully automated design of SCE VLSI circuits and processors on chip. The ac- and dc-biased SFQ logic families (such as RSFQ, ERSFQ, and AQFP) are, however, fundamentally different from CMOS logic families, for example, in terms of their reliance on two-terminal Josephson junctions with complex voltage-current (current-phase) behavior, cryogenic operation, pulse-based signaling, prevalence of inductors as key passive element, clocked nature of most logic cells and need for path balancing, limited fanout count of typically 2 or 3, use of biasing currents as the power source, etc. This tutorial aims at introducing the SCE SFQ technology starting from JJ device modeling and simulation to compact modeling of logic cells and superconductive transmission lines, to specialized logic synthesis, clock tree synthesis, bias distribution, and place&route engines.

TimeLabelPresentation Title
Authors
17:004.8.1PHYSICS-BASED MODELING AND DEVICE SIMULATION OF JJ'S
Author:
Pooya Jannati, Synopsys, US
Abstract
tbd
17:304.8.2ARCHITECTURES, SYNTHESIS FLOW, AND PLACE & ROUTE ENGINE FOR DC-BIASED SFQ LOGIC CIRCUITS
Author:
Massoud Pedram, USC, US
Abstract
tbd
18:004.8.3LIBRARY DESIGN AND DESIGN TOOLS FOR ADIABATIC QUANTUM-FLUX-PARAMETRON LOGIC CIRCUITS (AC-BIASED SFQ LOGIC)
Author:
Nobuyuki Yoshikawa, Yokohama National University, JP
Abstract
tbd
18:30End of session
Exhibition Reception in Exhibition Area

The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees.