4.2 Logic, Interconnects, Neurons: New Realizations

Printer-friendly version PDF version

Date: Tuesday, March 28, 2017
Time: 17:00 - 18:30
Location / Room: 4BC

Chair:
Elena Gnani, University of Bologna, IT, Contact Elena Gnani

Co-Chair:
Aida Todri-Sanial, CNRS-LIRMM, FR, Contact Aida Todri

This session covers papers showing new approaches to realize optimized logic circuit using silicon nanowire reconfigurable transistors; intra- and inter-core optoelectronic interconnects for energy efficient communications; and magnetic skyrmions as novel nanoelectronic device for non-linear neuron networks.

TimeLabelPresentation Title
Authors
17:004.2.1EXPLOITING TRANSISTOR-LEVEL RECONFIGURATION TO OPTIMIZE COMBINATIONAL CIRCUITS (Paper/SoftConf ID: 375)
Speaker:
Michael Raitza, TU Dresden, DE
Authors:
Michael Raitza1, Jens Trommer2, Akash Kumar3, Marcus Völp4, Dennis Walter5, Walter Weber6 and Thomas Mikolajick7
1Technische Universität Dresden and CfAED, DE; 2Namlab gGmbH, DE; 3Technische Universitaet Dresden, DE; 4SNT University of Luxembourg, LU; 5Technische Universität Dresden, DE; 6NaMLab gGmbH and CfAED, DE; 7NaMLab Gmbh / TU Dresden, DE
Abstract
Silicon nanowire reconfigurable field effect transistors (SiNW RFETs) abolish the physical separation of n-type and p-type transistors by taking up both roles in a configurable way within a doping-free technology. However, the potential of transistor-level reconfigurability has not been demonstrated in larger circuits, so far. In this paper, we present first steps to a new compact and efficient design of combinational circuits by employing transistor-level reconfiguration. We contribute new basic gates realized with silicon nanowires, such as 2/3-XOR and MUX gates. Exemplifying our approach with 4-bit, 8-bit and 16-bit conditional carry adders, we were able to reduce the number of transistors to almost one half. With our current case study we show that SiNW technology can reduce the required chip area by 16 %, despite larger size of the individual transistor, and improve circuit speed by 26 %.

Download Paper (PDF; Only available from the DATE venue WiFi)
17:304.2.2AUTOMATIC PLACE-AND-ROUTE OF EMERGING LED-DRIVEN WIRES WITHIN A MONOLITHICALLY-INTEGRATED CMOS+III-V PROCESS (Paper/SoftConf ID: 74)
Speaker:
Tushar Krishna, Georgia Institute of Technology, US
Authors:
Tushar Krishna1, Arya Balachandran2, Siau Ben Chiah2, Li Zhang3, Bing Wang3, Cong Wang2, Kenneth Lee Eng Kian3, Jurgen Michel4 and Li-Shiuan Peh5
1Georgia Institute of Technology, US; 2NTU, SG; 3SMART, SG; 4MIT, US; 5Professor, National University of Singapore, SG
Abstract
We leverage a recently demonstrated CMOS compatible III- V and Si monolithic integrated process to design photonic links comprising LEDs and photodiodes, as direct replacements for on- chip electrical wires. To enable VLSI-scale design of chips with such LED links, we create a library of opto-electronic standard cells, and model waveguides as traditional metal layers. This lets us integrate LED links into a commercial place-and-route tool, which treats them as electrical cells and wires for the most part, reducing design effort. We also add support for automated replacement of electrical nets with LED links. We find that LED-interconnect based designs substantially lower energy consumption vs. electrical copper wires (~39% reduction in the Network-on-Chip, ~27% reduction within a processor core) while achieving the same latency and bandwidth, demonstrating the promise of LED on-chip interconnects.

Download Paper (PDF; Only available from the DATE venue WiFi)
18:004.2.3A TUNABLE MAGNETIC SKYRMION NEURON CLUSTER FOR ENERGY EFFICIENT ARTIFICIAL NEURAL NETWORK (Paper/SoftConf ID: 477)
Speaker:
Deliang Fan, University of Central Florida, US
Authors:
Zhezhi He1 and Deliang Fan2
1Department of ECE, University of Central Florida, US; 2University of Central Florida, US
Abstract
Artificial neuron is one of the fundamental computing unit in brain-inspired artificial neural network. The standard CMOS based artificial neuron designs to implement non-linear neuron activation function typically consist of large number of transistors, which inevitably causes large area and power consumption. There is a need for novel nanoelectronic device that can intrinsically and efficiently implement such complex non-linear neuron activation function. Magnetic skyrmions are topologically stable chiral spin textures due to Dzyaloshinskii-Moriya interaction in bulk magnets or magnetic thin films. They are promising next-generation information carrier owing to ultra-small size (sub-10nm), high speed (>100m/s) with ultra-low depinning current density(MA/cm^2) and high defect tolerance compared to conventional magnetic domain wall motion devices. In this work, to the best of our knowledge, we are the first to propose a threshold-tunable artificial neuron based on magnetic skyrmion. Meanwhile, we propose a Skyrmion Neuron Cluster (SNC) to approximate non-linear soft-limiting neuron activation functions, such as the most popular sigmoid function. The device to system simulation indicates that our proposed SNC leads to 98.74% recognition accuracy in deep learning Convolutional Neural Network (CNN) with MNIST handwritten digits dataset. Moreover, the energy consumption of our proposed SNC is only 3.1 fJ/step, which is more than two orders lower than that of CMOS counterpart.

Download Paper (PDF; Only available from the DATE venue WiFi)
18:30IP2-1, 19COMPACT MODELING AND CIRCUIT-LEVEL SIMULATION OF SILICON NANOPHOTONIC INTERCONNECTS
Speaker:
Yuyang Wang, UC Santa Barbara, US
Authors:
Rui Wu1, Yuyang Wang2, Zeyu Zhang2, Chong Zhang2, Clint Schow2, John Bowers2 and Kwang-Ting Cheng2
1UC Santa Barbara, US; 2UCSB, US
Abstract
Nanophotonic interconnects have been playing an increasingly important role in the datacom regime. Greater integration of silicon photonics demands modeling and simulation support for design validation, optimization and design space exploration. In this work, we develop compact models for a number of key photonic devices, which are extensively validated by the measurement data of a fabricated optical network-on-chip (ONoC). Implemented in SPICE-compatible Verilog-A, the models are used in circuit-level simulations of full optical links. The simulation results match well with the measurement data. Our model library and simulation approach enable the electro-optical (EO) co-simulation, allowing designers to include photonic devices in the whole system design space, and to co-optimize the transmitter, interconnect, and receiver jointly.

Download Paper (PDF; Only available from the DATE venue WiFi)
18:31IP2-2, 320A TRUE RANDOM NUMBER GENERATOR BASED ON PARALLEL STT-MTJS
Speaker:
Yuanzhuo Qu, University of Alberta, CA
Authors:
Yuanzhuo Qu1, Jie Han1, Bruce Cockburn1, Yue Zhang2, Weisheng Zhao2 and Witold Pedrycz1
1University of Alberta, CA; 2Beihang University, CN
Abstract
Random number generators are an essential part of cryptographic systems. For the highest level of security, true random number generators (TRNG) are needed instead of pseudo-random number generators. In this paper, the stochastic behavior of the spin transfer torque magnetic tunnel junction (STT-MTJ) is utilized to produce a TRNG design. A parallel structure with multiple MTJs is proposed that minimizes device variation effects. The design is validated in a 28-nm CMOS process with Monte Carlo simulation using a compact model of the MTJ. The National Institute of Standards and Technology (NIST) statistical test suite is used to verify the randomness quality when generating encryption keys for the Transport Layer Security or Secure Sockets Layer (TLS/SSL) cryptographic protocol. This design has a generation speed of 177.8 Mbit/s, and an energy of 0.64 pJ is consumed to set up the state in one MTJ.

Download Paper (PDF; Only available from the DATE venue WiFi)
18:32IP2-3, 810ENABLING AREA EFFICIENT RF ICS THROUGH MONOLITHIC 3D INTEGRATION
Speaker:
Panagiotis Chaourani, KTH, Royal Institute of Technology, Stockholm, SE
Authors:
Panagiotis Chaourani, Per-Erik Hellström, Saul Rodriguez, Raul Onet and Ana Rusu, KTH, Royal Institute of Technology, SE
Abstract
The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

Download Paper (PDF; Only available from the DATE venue WiFi)
18:33IP2-4, 811RECONFIGURABLE THRESHOLD LOGIC GATES USING OPTOELECTRONIC CAPACITORS
Speaker:
Baris Taskin, Drexel University, US
Authors:
Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, Drexel University, US
Abstract
This paper investigates the integration of optoelectronic devices with CMOS threshold logic gates to design reconfigurable Boolean functions. The weight of the optoelectronic device can be altered by changing the optical power which is used to reconfigure the threshold logic (TL) gate. The proposed optoelectronic capacitor based TL (OECTL) gates are designed for i) simplistic AND/NAND gates and OR/NOR gates with large fan-in and ii) linearly separable Boolean functions that can be reconfigured to other linearly separable Boolean functions, constrained in reconfiguration by the specifics of TL operation. SPICE simulations in 65nm bulk CMOS technology with a Verilog-A model for the optoelectronic capacitor demonstrate i) AND/NAND gates and OR/NOR gates are 2X faster as fan0in increases and consumes low power ii) Boolean function can be reconfigured with 0.58X smaller delay and 0.46X lesser power of standard CMOS.

Download Paper (PDF; Only available from the DATE venue WiFi)
18:30End of session
Exhibition Reception in Exhibition Area
The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees.