12.2 Advances in Microfluidics and Neuromorphic Architectures

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Date: Thursday, March 30, 2017
Time: 16:00 - 17:30
Location / Room: 4BC

Chair:
Tsung-Yi Ho, National Tsing Hua University, TW, Contact Tsung-Yi Ho

Co-Chair:
Li Jiang, Shanghai Jiao Tong University, CN, Contact Li Jiang

This session consists of four presentations from emerging applications in EDA such as mircrofluidics and neural networks. The first presentation proposes a progressive optimization procedure for the synthesis of fault-tolerant flow-based microfluidics. The second presentation presents a hybrid microfluidic platform that enables single-cell analysis on a heterogeneous cells. Next presentation discusses automatic verification on networked labs-on-chip architecture. The final presentation proposes synthesis method for parallel convolutional layers of convolutional neural network.

TimeLabelPresentation Title
Authors
16:0012.2.1FAST ARCHITECTURE-LEVEL SYNTHESIS OF FAULT-TOLERANT FLOW-BASED MICROFLUIDIC BIOCHIPS (Paper/SoftConf ID: 534)
Speaker:
Tsung-Yi Ho, National Tsing Hua University, TW
Authors:
Wei-Lun Huang1, Ankur Gupta2, Sudip Roy2, Tsung-Yi Ho1 and Paul Pop3
1National Tsing Hua University, TW; 2Indian Institute of Technology Roorkee, IN; 3Technical University of Denmark, DK
Abstract
Microfluidic-based lab-on-a-chips have emerged as a popular technology for implementation of different biochemical test protocols used in medical diagnostics. However, in the manufacturing process or during operation of such chips, some faults may occur that leads to damage of the chip, which in turn results in wastage of expensive reagent fluids. In order to make the chip fault-tolerant, the state-of-the-art technique adopts simulated annealing (SA) based approach to synthesize a fault-tolerant architecture. However, the SA method is time consuming and non-deterministic with over-simplified model that usually derive sub-optimal results. Thus, we propose a progressive optimization procedure for the synthesis of fault-tolerant flow-based microfluidic biochips. Simulation results demonstrate that our method is efficient compared to the state-of-the-art techniques and can provide near-optimal and effective solutions in 88% (on average) less CPU time compared to state-of-the-art technique over three benchmark bioprotocols.

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16:3012.2.2COSYN: EFFICIENT SINGLE-CELL ANALYSIS USING A HYBRID MICROFLUIDIC PLATFORM (Paper/SoftConf ID: 460)
Speaker:
Mohamed Ibrahim, Duke University, US
Authors:
Mohamed Ibrahim1, Krishnendu Chakrabarty1 and Ulf Schlichtmann2
1Duke University, US; 2TU M√ľnchen, DE
Abstract
Single-cell genomics is used to advance our understanding of diseases such as cancer. Microfluidic solutions have recently been developed to classify cell types or perform single-cell biochemical analysis on pre-isolated types of cells. However, new techniques are needed to efficiently classify cells and conduct biochemical experiments on multiple cell types concurrently. System integration and design automation are major challenges in this context. To overcome these challenges, we present a hybrid microfluidic platform that enables complete single-cell analysis on a heterogeneous pool of cells. We combine this architecture with an associated design-automation and optimization framework, referred to as Co-Synthesis (CoSyn). The proposed framework employs real-time resource allocation to coordinate the progression of concurrent cell analysis. Simulation results show that CoSyn efficiently utilizes platform resources and outperforms baseline techniques.

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17:0012.2.3VERIFICATION OF NETWORKED LABS-ON-CHIP ARCHITECTURES (Paper/SoftConf ID: 635)
Speaker:
Andreas Grimmer, Johannes Kepler University of Linz, AT
Authors:
Andreas Grimmer1, Werner Haselmayr1, Andreas Springer1 and Robert Wille2
1Johannes Kepler University, AT; 2Johannes Kepler University Linz, AT
Abstract
Labs-on-Chips (LoCs) revolutionize conventional biochemical processes and may even replace laboratories by integrating and minimizing their functionalities on a single chip. In a promising and emerging realization of LoCs, small volumes of reagents, so-called droplets, transport the biological sample and flow in closed channels of sub-millimeter diameters. This realization is called Networked Labs-on-Chips (NLoCs). The architecture of an NLoC defines different paths through which the droplets can flow. These paths are realized by splitting channels into multiple successor channels - so-called bifurcations. However, whether the architecture indeed allows to route droplets along the desired paths and, hence, correctly executes the intended experiment is not guaranteed. In this work, we present the first automatic solution for verifying whether an NLoC architecture allows to correctly route the droplets. Our evaluations demonstrate the applicability and importance of the proposed solution on a set of NLoC architectures.

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17:1512.2.4SYNTHESIS OF ACTIVATION-PARALLEL CONVOLUTION STRUCTURES FOR NEUROMORPHIC ARCHITECTURES (Paper/SoftConf ID: 603)
Speaker:
Seban Kim, Incheon National University, KR
Authors:
Seban Kim and Jaeyong Chung, Incheon National University, KR
Abstract
Convolutional neural networks have demonstrated continued success in various visual recognition challenges. The convolutional layers are implemented in the activation-serial or fully parallel manner on neuromorphic computing systems. This paper presents an unrolling method that generates parallel structures for the convolutional layers depending on a required level of parallel processing. We analyze the resource requirements for the unrolling of the two-dimensional filters, and propose methods to deal with practical considerations such as stride, borders, and alignment. We apply the propose methods to practical convolutional neural networks including AlexNet and the generated structures are mapped onto a recent neuromorphic computing system. This demonstrates that the proposed methods can improve the performance or reduce the power consumption significantly even without area penalty.

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17:30End of session