11.6 Design Automation Solutions for Microfluidic Platforms and Tasks

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Date: Thursday, March 28, 2019
Time: 14:00 - 15:30
Location / Room: Room 6

Chair:
Robert Wille, Johannes Kepler University Linz, AT, Contact Robert Wille

Co-Chair:
Andy Tyrrell, University of York, GB, Contact Andy Tyrrell

The session provides talks on design automation for microfluidic devices which covers both, a wide range of different platforms and tasks. More precisely, the presentations are covering platforms such as biochips based on micro-electrode-dot arrays (MEDA biochips), flow-based biochips, and Programmable Microfluidic Devices (PMDs). The covered tasks include parameter space exploration, physical synthesis, and washing. This variety makes this session ideal for both, experts already working in the area and interest in the latest results but also researchers who are curios about this domain and want to get a closer insight.

TimeLabelPresentation Title
Authors
14:0011.6.1BIOSCAN: PARAMETER-SPACE EXPLORATION OF SYNTHETIC BIOCIRCUITS USING MEDA BIOCHIPS
Speaker:
Mohamed Ibrahim, Intel Corporation, US
Authors:
Mohamed Ibrahim1, Bhargab Bhattacharya2 and Krishnendu Chakrabarty1
1Duke University, US; 2Indian Statistical Institute, Kolkata, IN
Abstract
Recent advances in microfluidic technology offer efficient platforms to emulate complex molecular networks of biological pathways (biocircuits) on a lab-on-chip. The behavior of biocircuits is governed by a number of gene-regulatory parameters. A fundamental challenge in synthesizing and verifying biocircuits is the lack of design tools that implement biocircuit-regulatory scanning (BRS) assays to explore the large parameter-space efficiently, while optimizing synthesis time and reagent cost. In this paper, we introduce an optimization flow named BioScan for systematic exploration of the parameter-space of a biocircuit. BioScan includes: (1) a statistical approach to determine a subset of mixing ratios of reagents that span the entire parameter space as densely as possible subject to certain cost constraints; (2) an ILP-based synthesis method that implements a BRS-assay on a micro-electrode dot-array biochip. Simulation results show that BioScan reduces reagent cost and enhances space-filling properties.
14:3011.6.2PHYSICAL SYNTHESIS OF FLOW-BASED MICROFLUIDIC BIOCHIPS CONSIDERING DISTRIBUTED CHANNEL STORAGE
Speaker:
Xing Huang, National Tsing Hua University, TW
Authors:
Zhisheng Chen1, Xing Huang2, Wenzhong Guo3, Bing Li4, Tsung-Yi Ho2 and Ulf Schlichtmann4
1Fuzhou University, CN; 2National Tsing Hua University, TW; 3Department of Mathematics and Computer Science, Fuzhou University, CN; 4TUM, DE
Abstract
Flow-based microfluidic biochips (FBMBs) have attracted much attention over the past decade. On such a micrometer-scale platform, various biochemical applications, also called bioassays, can be processed concurrently and automatically. To improve execution efficiency and reduce fabrication cost, a distributed channel-storage architecture (DCSA) can be implemented on this platform, where fluid samples can be cached temporarily in flow channels close to components. Although this distributed storage architecture can improve the execution efficiency of FBMBs significantly, it requires a careful arrangement of fluid samples to enable the channels to fulfill the dual functions of transportation and caching. In this paper, we formulate the first practical flow-layer physical design problem considering DCSA, and propose a top-down synthesis algorithm to generate efficient solutions considering execution efficiency, washing, and resource usage simultaneously. Experimental results demonstrate that the proposed algorithm leads to a shorter execution time, less flowchannel length, and a higher efficiency of on-chip resource utilization for biochemical applications compared with a direct approach to incorporate distributed storage into existing frameworks.
15:0011.6.3BLOCK-FLUSHING: A BLOCK-BASED WASHING ALGORITHM FOR PROGRAMMABLE MICROFLUIDIC DEVICES
Speaker:
Bing Li, TUM, DE
Authors:
Yu-Huei Lin1, Tsung-Yi Ho1, Bing Li2 and Ulf Schlichtmann2
1National Tsing Hua University, TW; 2TUM, DE
Abstract
Programmable Microfluidic Devices (PMDs) have emerged as a new architecture for next-generation flow-based biochips. These devices can be dynamically reconfigured to execute different bioassays flexibly and efficiently owing to their two- dimensional regularly-arranged valve structure. During execution of a bioassay or between the execution of multiple bioassays, some areas on the PMD, however, become contaminated and must be cleaned by washing them with a buffer flow before they are reused. In this paper, we propose a novel block-based washing technique called block flushing. In this method, contaminated areas are first collected according to given patterns and flushed as a whole to increase washing efficiency. Simulation results show that with this technique the proposed method can achieve on average 28% improvement in reducing washing time compared with two other baseline solutions.
15:30IP5-13, 916A PULSE WIDTH MODULATION BASED POWER-ELASTIC AND ROBUST MIXED-SIGNAL PERCEPTRON DESIGN
Speaker:
Sergey Mileiko, MR, GB
Authors:
Sergey Mileiko1, Rishad Shafik1, Alex Yakovlev1 and Jonathan Edwards2
1Newcastle University, GB; 2Temporal Computing, GB
Abstract
Neural networks are exerting burgeoning influence in emerging artificial intelligence applications at the micro-edge, such as sensing systems. As many of these systems are typically self-powered, their circuits are expected to be resilient and efficient to continuous power variations imposed by the harvesters. In this paper, we propose a novel mixed-signal (i.e. analogue/digital) approach of designing a power-elastic perceptron using the principle of pulse width modulation (PWM). Fundamental to the design are a number of parallel inverters that transcode the input-weight pairs based on the principle of PWM duty cycle. Since PWM-based inverters are typically resilient to amplitude and frequency variations, the perceptron shows a high degree of power elasticity and robustness in the presence of these variations. Our extensive design analysis also demonstrates significant power and area efficiency, leading to significant reduction in dynamic and leakage energy when compared with a purely digital equivalent.
15:31IP5-14, 320FAULT LOCALIZATION IN PROGRAMMABLE MICROFLUIDIC DEVICES
Speaker:
Ulf Schlichtmann, TUM, DE
Authors:
Alessandro Bernardini, Chunfeng Liu, Bing Li and Ulf Schlichtmann, TUM, DE
Abstract
Programmable Microfluidic Devices (PMDs) have revolutionized the traditional biochemical experiment flow. Test algorithms for PMDs have recently been proposed. Test patterns can be generated algorithmically. But an algorithm for fault localization once some faults have been identified is not yet available. When testing a PMD, once a test pattern fails it is unknown where the stuck valve is located. The stuck valve can be any one valve out of many valves forming the test pattern. In this paper, we propose an effective algorithm for the localization of stuck-at-0 faults and stuck-at-1 faults in a PMD. The stuck valve is localized either exactly or within a very small set of candidate valves. Once the locations of faulty valves are known, it becomes possible to continue to use the PMD by resynthesizing the application
15:32IP5-15, 529THERMAL SENSING USING MICRO-RING RESONATORS IN OPTICAL NETWORK-ON-CHIP
Speaker:
Mengquan Li, Chongqing University, CN
Authors:
Weichen Liu1, Mengquan Li2, Wanli Chang3, Chunhua Xiao2, Yiyuan Xie4, Nan Guan5 and Lei Jiang6
1Nanyang Technological University, SG; 2Chongqing University, CN; 3University of York, GB; 4Southwest University, CN; 5Hong Kong Polytechnic University, HK; 6Indiana University Bloomington, US
Abstract
In this paper, we for the first time utilize the micro-ring resonators (MRs) in optical networks-on-chip (ONoCs) to implement thermal sensing without requiring additional hardware or chip area. The challenges in accuracy and reliability that arise from fabrication-induced process variations (PVs) and device-level wavelength tuning mechanism are resolved.We quantitatively model the intrinsic thermal sensitivity of MRs with fine-grained consideration of wavelength tuning mechanism. Based on it, a novel PV-tolerant thermal sensor design is proposed. By exploiting the hidden 'redundancy' in wavelength division multiplexing (WDM) technique, our sensor achieves accurate and efficient temperature measurement with the capability of PV tolerance. Evaluation results based on professional photonic component and circuit simulations show an average of 86.49% improvement in measurement accuracy compared to the state-of-the-art on-chip thermal sensing approach using MRs. Our thermal sensor achieves stable performance in the ONoCs employing dense WDM with an inaccuracy of only 0.8650 K.
15:33IP5-16, 59ADIABATIC IMPLEMENTATION OF MANCHESTER ENCODING FOR PASSIVE NFC SYSTEM
Speaker:
Sachin Maheshwari, University of Westminster, GB
Authors:
Sachin Maheshwari1 and Izzet Kale2
1university of Westminster, GB; 2University of Westminster, GB
Abstract
Energy plays an important role in NFC passive tags as they are powered by radio waves from the reader. Hence reducing the energy consumption of the tag can bring large interrogation range, increase security and maximizes the reader's battery life. The ISO 14443 standard utilizes Manchester coding for the data transmission from passive tag to the reader in the majority of the cases for NFC passive communications. This paper proposes a novel method of Manchester encoding using the adiabatic logic technique for energy minimization. The design is implemented by generating replica bits of the actual transmitted bits and then flipping the replica bits, for generating the Manchester coded bits. The proposed design was implemented using two adiabatic logic families namely; Positive Feedback Adiabatic Logic (PFAL) and Improved Efficient Charge Recovery Logic (IECRL) which are compared in terms of energy for the range of frequency variations. The energy comparison was also made including the power-clock generator designed using 2-stepwise charging circuit (SWC) with FSM controller. The simulation results presented for 180nm CMOS technology at 1.8V power supply shows that IECRL shows approximately 40% less system energy compared to PFAL family.
15:30End of session
Coffee Break in Exhibition Area



Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Lunch Breaks (Lunch Area)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 26, 2019

Wednesday, March 27, 2019

Thursday, March 28, 2019