[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

- Abadir, M.S.
- Measuring the Effectiveness of Various Design Validation Approaches for PowerPC
^{TM}Microprocessor Arrays [p 273] - Adler, T.
- An Interactive Router for Analog IC Design [p 414]
- Agsteiner, K.
- An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
- Al-Khalili, D.
- VHDL Modelling and Analysis of Fault Secure Systems [p 148]
- Allara, A.
- A Model for System-Level Timed Analysis and Profiling [p 204]
- Andrews, M.
- Power and Timing Modeling for ASIC Designs [p 969]
- Antola, A.
- A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
- Aourid, S.
- Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
- Arsintescu, B.G.
- Constraints Space Management for the Layout of Analog IC's [p 971]
- Artigas, J.I.
- VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
- Arts, H.
- PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
- Arz, U.
- Core Interconnect Testing Hazards [p 953]
- Auvergne, D.
- Temperature Effect on Delay for Low Voltage Applications [p 680]
- Avedillo, M.J.
- A Dynamic Model for the State Assignment Problem [p 835]
- Ayuda, L.
- VHDL Teamwork, Organization Units and Workspace Management [p 297]
- Azaïs, F.
- Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]

- Banerjee, P.
- PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
- Barke, E.
- A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances [p 649]
- Path Verification Using Boolean Satisfiability [p 965]
- Barragán, L.A.
- VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
- Barriga, A.
- XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
- Basu, A.
- Register-Constrained Address Computation in DSP Programs [p 929]
- Baur, U.
- A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
- Becker, U.
- A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
- Benini, L.
- Characterization-Free Behavioral Power Modeling [p 767]
- Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
- Berkelaar, M.R.C.M.
- An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
- Bertrand, Y.
- Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]
- Bisdounis, L.
- Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
- Blaauw, D.
- CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
- Bogliolo, A.
- Characterization-Free Behavioral Power Modeling [p 767]
- Bogue, T.
- Built-In Self-Test with an Alternating Output [p 180]
- Bolchini, C.
- Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
- Böttger, J.
- An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
- Brayton, R.K.
- Combinational Verification Based on High-Level Functional Specifications [p 803]
- Breuer, M.A.
- Scheduling and Module Assignment for Reducing BIST Resources [p 66]
- Brglez, F.
- Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
- Bringmann, O.
- Cross-Level Hierarchical High-Level Synthesis [p 451]
- Buchenrieder, K.
- A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]

- Calin, T.
- Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
- Calvez, J.P.
- A Programmable Multi-Language Generator for CoDesign [p 927]
- Carrabina-Bordoll, J.
- On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits [p 624]
- Castellví, A.
- Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
- Catthoor, F.
- Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology Versus Design Methodology Solutions [p 709]
- Cerny, E.
- Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
- Chakradhar, S.T.
- State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits [p 577]
- Chandramouli, V.
- AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
- Chang, D.
- Functional Scan Chain Testing [p 278]
- Chang, S.-C.
- On Removing Multiple Redundancies in Combinational Circuits [p 738]
- Chatzigeorgiou, A.
- Collapsing the Transistor Chain to an Effective Single Equivalent Transistor [p 2]
- Chen, C.-T.
- Architectural Rule Checking for High-Level Synthesis [p 949]
- Chen, R.M.M.
- MCM Interconnect Design Using Two-Pole Approximation [p 544]
- Cheng, D.I.
- On Removing Multiple Redundancies in Combinational Circuits [p 738]
- Cheng, K.-T.
- Functional Scan Chain Testing [p 278]
- Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits [p 698]
- Cheung, H.
- Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
- Choi, H.
- Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
- Chou, M.
- Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
- Chu, C.C.N.
- A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing [p 479]
- Conradi, P.
- A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
- Coors, M.
- FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
- Coppens, J.
- VHDL Modelling and Analysis of Fault Secure Systems [p 148]
- Corno, F.
- Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
- Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
- Cortadella, J.
- Efficient Encoding Schemes for Symbolic Analysis of Petri Nets [p 790]
- Costa, J.P.
- Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
- Cota, E.F.
- Microsystems Testing: An Approach and Open Problems [p 524]
- Coudert, O.
- A New Paradigm for Dichotomy-Based Constrained Encoding [p 830]
- Courtois, B.
- Microsystems Testing: An Approach and Open Problems [p 524]
- Crespo, J.
- ATM Traffic Shaper: ATS [p 96]
- Crossland, W.A.
- Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]

- Daga, J.M.
- Temperature Effect on Delay for Low Voltage Applications [p 680]
- Dave, B.P.
- CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures [p 118]
- de Armas, V.
- A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
- de Jong, G.
- Efficient Verification Using Generalized Partial Order Analysis [p 782]
- de la Torre, E.
- Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
- De Loore, B.
- IP-Based System-on-a-Chip Design [p 290]
- De Micheli, G.
- Characterization-Free Behavioral Power Modeling [p 767]
- Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
- Deicke, J.
- From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
- Dharchoudhury, A.
- CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
- Diaz, J.C.
- ATM Traffic Shaper: ATS [p 96]
- Doboli, A.
- Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
- Donnay, S.
- Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
- Drechsler, R.
- Dynamic Minimization of Word-Level Decision Diagrams [p 612]
- Dröge, G.
- EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
- Duarte, R.O.
- Design of Fault-Secure Parity-Prediction Booth Multipliers [p 7]
- Dutt, N.D.
- Data Cache Sizing for Embedded Processor Applications [p 925]

- Ecküller, J.
- Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
- Economakos, G.
- AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]
- Eles, P.
- Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
- Ellis, A.
- Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
- Eppler, W.
- High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
- Eshraghian, K.
- Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]

- Fassnacht, U.
- Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset [p 325]
- Favalli, M.
- Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
- Feldmann, P.
- Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Padé Approximation [p 530]
- Fernández, M.
- Correct High-Level Synthesis: A Formal Perspective [p 977]
- Ferrandi, F.
- Power Estimation of Behavioral Descriptions [p 762]
- Figueras, J.
- RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
- Estimation of the Defective I
_{DDQ}Caused by Shorts in Deep-Submicron CMOS ICs [p 490] - Fischer, T.
- High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
- Flottes, M.L.
- Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
- Fornaciari, W.
- A Model for System-Level Timed Analysis and Profiling [p 204]
- Freund, R.W.
- Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Padé Approximation [p 530]
- Fummi, F.
- Power Estimation of Behavioral Descriptions [p 762]
- Furber, S.B.
- The Design of an Asynchronous VHDL Synthesizer [p 44]

- García, J.I.
- VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
- García, M.
- Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
- Garte, D.
- A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
- Gasteier, M.
- Generation of Interconnect Topologies for Communication Synthesis [p 36]
- Gemmeke, H.
- High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
- Gerlach, J.
- A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment [p 226]
- Ghosh, D.
- Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
- Gielen, G.
- Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
- Glesner, M.
- Generation of Interconnect Topologies for Communication Synthesis [p 36]
- Goldberg, E.I.
- Combinational Verification Based on High-Level Functional Specifications [p 803]
- Gómez, J.-A.
- Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
- Gong, J.
- Architectural Rule Checking for High-Level Synthesis [p 949]
- Gössel, M.
- Built-In Self-Test with an Alternating Output [p 180]
- Goutis, C.E.
- Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
- Gräb, H.
- Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
- Grabinski, H.
- Core Interconnect Testing Hazards [p 953]
- Graeb, H.E.
- Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
- Grimm, C.
- Repartitioning and Technology Mapping of Electronic Hybrid Systems [p 52]
- Grode, J.
- Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
- Gröpl, M.
- Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
- Grötker, T.
- A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
- Grout, I.
- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
- Gschwind, M.
- Hardware/Software Co-Design of a Fuzzy RISC Processor [p 875]
- Guo, R.
- Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]
- Gupta, R.K.
- An Algorithm to Determine Mutually Exclusive Operations in Behavioral Descriptions [p 457]
- Gupta, S.K.
- Scheduling and Module Assignment for Reducing BIST Resources [p 66]

- Ha, S.
- Optimized Timed Hardware Software Cosimulation without Roll-Back [p 945]
- Haase, J.
- A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
- Hagelauer, R.
- Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base [p 931]
- Hamilton, S.N.
- Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs [p 604]
- Hansen, C.
- Verification by Simulation Comparison Using Interface Synthesis [p 436]
- Harlow III, J.
- Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
- Hedrich, L.
- A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances [p 649]
- Hein, S.
- Embedded DRAM Architectural Trade-Offs [p 704]
- Heineken, H.T.
- Design-Manufacturing Interface: Part I -- Vision [p 550]
- Design-Manufacturing Interface: Part II -- Applications [p 557]
- Performance-Manufacturability Tradeoffs in IC Design [p 563]
- Hellebrand, S.
- Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
- Heller, D.
- A Programmable Multi-Language Generator for CoDesign [p 927]
- Helvig, C.S.
- Improved Approximation Bounds for the Group Steiner Problem [p 406]
- Hemani, A.
- Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
- Hermida, R.
- Correct High-Level Synthesis: A Formal Perspective [p 977]
- Hetzel, A.
- A Sequential Detailed Router for Huge Grid Graphs [p 332]
- Higuchi, K.
- Innovative System-Level Design Environment Based on FORM for Transport Processing System [p 883]
- Hollstein, T.
- From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
- Höreth, S.
- Dynamic Minimization of Word-Level Decision Diagrams [p 612]
- Horneber, E.-H.
- EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
- Hsiao, M.S.
- State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits [p 577]
- Hsieh, Y.-W.
- Model Abstraction for Formal Verification [p 140]
- Huertas, J.L.
- Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
- A Dynamic Model for the State Assignment Problem [p 835]
- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
- Huss, S.A.
- A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks [p 721]
- Hwang, S.H.
- Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]

- Iglesias, C.A.
- A Knowledge-Based System for Hardware-Software Partitioning [p 914]
- Inoue, A.
- Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
- Ishihara, T.
- Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
- Iyenaga, N.
- A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator [p 951]
- Izaguirre, I.
- VHDL Teamwork, Organization Units and Workspace Management [p 297]

- Jemai, A.
- Architectural Simulation in the Context of Behavioral Synthesis [p 590]
- Jerraya, A.A.
- Architectural Simulation in the Context of Behavioral Synthesis [p 590]
- Jess, J.A.G.
- Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
- A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
- Jha, N.K.
- CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures [p 118]
- IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
- Jiang, Y.-M.
- Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits [p 698]
- Jiménez, C.J.
- XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
- Jochens, G.
- Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
- Johannes, F.M.
- Technology Mapping for Minimizing Gate and Routing Area [p 664]
- Jürgensen, H.
- Built-In Self-Test with an Alternating Output [p 180]

- Kahng, A.B.
- Interconnect Tuning Strategies for High-Performance ICs [p 471]
- Kamon, M.
- An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
- Kapur, N.
- Kassab, M.
- Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
- Kaul, M.
- Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures [p 389]
- Kayss, M.
- From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
- Kazmierski, T.
- A Formal Description of VHDL-AMS Analogue Systems [p 916]
- Fuzzy-Logic Digital-Analogue Interfaces for Accurate Mixed-Signal Simulation [p 941]
- Keding, H.
- FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
- Khare, J.
- Design-Manufacturing Interface: Part I -- Vision [p 550]
- Design-Manufacturing Interface: Part II -- Applications [p 557]
- Khouri, K.S.
- IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
- Kick, B.
- A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
- Kimura, H.
- A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator [p 951]
- Kission, P.
- Architectural Simulation in the Context of Behavioral Synthesis [p 590]
- Kitamura, F.
- PASTEL: A Parameterized Memory Characterization System [p 15]
- Kleine, U.
- Automatic Topology Optimization for Analog Module Generators [p 961]
- Knudsen, P.V.
- Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
- Koegst, M.
- A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
- Koehl, J.
- A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
- Kohno, M.
- PASTEL: A Parameterized Memory Characterization System [p 15]
- Kolsteren, M.A.J.
- An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
- Koufopavlou, O.
- Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
- Kovac, M.
- Universal Strong Encryption FPGA Core Implementation [p 923]
- Kress, R.
- A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]
- Krodel, T.
- Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
- Kropf, T.
- Formal Specification in VHDL for Hardware Verification [p 257]
- Kruse, L.
- Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
- Kuchcinski, K.
- Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
- Kücükcakar, K.
- Architectural Rule Checking for High-Level Synthesis [p 949]
- Kuh, E.S.
- A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction [p 466]
- Kukimoto, Y.
- Combinational Verification Based on High-Level Functional Specifications [p 803]
- Kumar, A.
- Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
- Kunzmann, A.
- Verification by Simulation Comparison Using Interface Synthesis [p 436]
- Kurdahi, F.J.
- Layout-Driven High Level Synthesis for FPGA Based Architectures [p 446]
- Kyung, C.-M.
- Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]

- Lachowicz, S.W.
- Lago, E.
- XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
- Lakshminarayana, G.
- IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
- Lee, M.T.-C.
- Functional Scan Chain Testing [p 278]
- Leijten, J.A.J.
- Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
- Leupers, R.
- Register-Constrained Address Computation in DSP Programs [p 929]
- Levitan, S.P.
- Model Abstraction for Formal Verification [p 140]
- Leyn, F.
- Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
- Li, J.
- An Algorithm to Determine Mutually Exclusive Operations in Behavioral Descriptions [p 457]
- Lin, B.
- Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling [p 211]
- Efficient Verification Using Generalized Partial Order Analysis [p 782]
- Lindenkreuz, T.
- Path Verification Using Boolean Satisfiability [p 965]
- Lindermeir, W.M.
- Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
- López, D.R.
- XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
- López, J.C.
- A Knowledge-Based System for Hardware-Software Partitioning [p 914]
- López, M.L.
- A Knowledge-Based System for Hardware-Software Partitioning [p 914]
- Lorenz, G.
- A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
- Lu, A.
- Technology Mapping for Minimizing Gate and Routing Area [p 664]
- Lubaszewski, M.
- Microsystems Testing: An Approach and Open Problems [p 524]
- Ludwig, T.
- A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]

- Macii, E.
- Power Estimation of Behavioral Descriptions [p 762]
- Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
- Madsen, J.
- Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
- Maestro, J.A.
- A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
- Maheshwari, N.
- Efficient Minarea Retiming of Large Level-Clocked Circuits [p 840]
- Maly, W.
- Design-Manufacturing Interface: Part I -- Vision [p 550]
- Design-Manufacturing Interface: Part II -- Applications [p 557]
- Performance-Manufacturability Tradeoffs in IC Design [p 563]
- Manhaeve, H.
- A Fully Digital Controlled Off-Chip I
_{DDQ}Measurement Unit [p 495] - IOCIMU -- An Integrated Off-Chip I
_{DDQ}Measurement Unit [p 959] - Marculescu, D.
- Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
- Marculescu, R.
- Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
- Marek-Sadowska, M.
- Functional Scan Chain Testing [p 278]
- Marques, N.
- An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
- Martin, G.
- Design Methodologies for System Level IP [p 286]
- Martin, H.-G.
- A Comparing Study of Technology Mapping for FPGA [p 939]
- Martínez, M.
- A Dynamic Model for the State Assignment Problem [p 835]
- Marwedel, P.
- Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems [p 912]
- Register-Constrained Address Computation in DSP Programs [p 929]
- Mecha, H.
- A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
- Menchikov, A.
- High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
- Mendías, J.M.
- Correct High-Level Synthesis: A Formal Perspective [p 977]
- Mesman, B.
- A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
- Metra, C.
- Novel Technique for Testing FPGAs [p 89]
- Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
- Meyr, H.
- FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
- Mir, S.
- Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
- Mittwollen, N.
- VHDL-AMS: The Missing Link in System Design -- Experiments with Unified Modelling in Automotive Engineering [p 59]
- Mojoli, G.
- Novel Technique for Testing FPGAs [p 89]
- Monjau, D.
- An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
- Montiel-Nelson, J.A.
- A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
- Moser, E.
- VHDL-AMS: The Missing Link in System Design -- Experiments with Unified Modelling in Automotive Engineering [p 59]
- Mozos, D.
- A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
- Mrva, M.
- Enhanced Reuse and Teamwork Capabilities for an Object-Oriented Extension of VHDL [p 250]
- A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]
- Muddu, S.
- Interconnect Tuning Strategies for High-Performance ICs [p 471]
- Müller, A.
- A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
- Muller, F.
- A Programmable Multi-Language Generator for CoDesign [p 927]
- Müller-Glaser, K.D.
- Advanced Optimistic Approaches in Logic Simulation [p 362]
- Müller-Wipperfürth, T.
- Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base [p 931]
- Münch, M.
- Generation of Interconnect Topologies for Communication Synthesis [p 36]
- Mutz, M.
- Register Transfer Level VHDL Models without Clocks [p 153]

- Nag, P.K.
- Design-Manufacturing Interface: Part I -- Vision [p 550]
- Design-Manufacturing Interface: Part II -- Applications [p 557]
- Nagoya, A.
- Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
- Naroska, E.
- Parallel VHDL Simulation [p 159]
- Navarro, D.
- Nebel, W.
- Object-Oriented Modelling of Parallel Hardware Systems [p 234]
- A Flexible Message Passing Mechanism for Objective VHDL [p 242]
- Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
- Neul, R.
- A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
- Nicolaidis, M.
- Design of Fault-Secure Parity-Prediction Booth Multipliers [p 7]
- Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
- Nicolau, A.
- Data Cache Sizing for Embedded Processor Applications [p 925]
- Nicoli, F.
- Denotational Semantics of a Behavioral Subset of VHDL [p 975]
- Niemann, R.
- Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems [p 912]
- Niggemeyer, D.
- Core Interconnect Testing Hazards [p 953]
- Nikolaidis, S.
- Collapsing the Transistor Chain to an Effective Single Equivalent Transistor [p 2]
- Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
- Nordholz, P.
- Core Interconnect Testing Hazards [p 953]
- Nourani, M.
- A Bypass Scheme for Core-Based System Fault Testing [p 979]
- Núnez, A.
- A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]

- Öberg, J.
- Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
- Ogawa, K.
- PASTEL: A Parameterized Memory Characterization System [p 15]
- Oh, J.
- Gated Clock Routing Minimizing the Switched Capacitance [p 692]
- Olcoz, S.
- VHDL Teamwork, Organization Units and Workspace Management [p 297]
- Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
- Orailoglu, A.
- Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs [p 604]
- Ottaviano, E.
- Temperature Effect on Delay for Low Voltage Applications [p 680]
- Otten, R.H.J.M.
- Constraints Space Management for the Layout of Analog IC's [p 971]
- Otterstedt, J.
- Core Interconnect Testing Hazards [p 953]
- Ouyang, C.
- Design-Manufacturing Interface: Part II -- Applications [p 557]
- Page, I.
- Design of Future Systems [p 343]

- Panda, P.R.
- Data Cache Sizing for Embedded Processor Applications [p 925]
- Panda, R.
- CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
- Papachristou, C.
- Testing DSP Cores Based on Self-Test Programs [p 166]
- A Bypass Scheme for Core-Based System Fault Testing [p 979]
- Papakonstantinou, G.
- AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]
- Park, I.-C.
- Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
- Parulkar, I.
- Scheduling and Module Assignment for Reducing BIST Resources [p 66]
- Pasquier, O.
- A Programmable Multi-Language Generator for CoDesign [p 927]
- Pastor, E.
- Efficient Encoding Schemes for Symbolic Analysis of Petri Nets [p 790]
- Pastore, S.
- Novel Technique for Testing FPGAs [p 89]
- Pedram, M.
- Gated Clock Routing Minimizing the Switched Capacitance [p 692]
- Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
- Penalba, O.
- VHDL Teamwork, Organization Units and Workspace Management [p 297]
- Peng, Z.
- An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis [p 74]
- Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
- Peralías, E.
- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
- Pflueger, T.
- A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
- Pires, R.
- Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
- Piuri, V.
- A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
- Plaza, P.
- ATM Traffic Shaper: ATS [p 96]
- Pomeranz, I.
- Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]
- A Synthesis Procedure for Flexible Logic Functions [p 973]
- Design-for-Testability for Synchronous Sequential Circuits Using Locally Available Lines [p 983]
- Poncino, M.
- Power Estimation of Behavioral Descriptions [p 762]
- Pop, P.
- Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
- Portal, J.M.
- RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
- Post, G.
- A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
- Prieto, J.A.
- Prihozhy, A.
- Asynchronous Scheduling and Allocation [p 963]
- Prinetto, P.
- Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
- Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
- Pullela, S.
- CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
- Putzke-Röming, W.
- A Flexible Message Passing Mechanism for Objective VHDL [p 242]
- Pyttel, A.
- PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]

- Rabaey, J.
- An Energy-Conscious Exploration Methodology for Reconfigurable DSPs [p 341]
- Rabe, D.
- Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
- Radetzki, M.
- A Flexible Message Passing Mechanism for Objective VHDL [p 242]
- Radhakrishnan, S.
- Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
- Rassau, A.M.
- Reddy, S.M.
- Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]
- A Synthesis Procedure for Flexible Logic Functions [p 973]
- Design-for-Testability for Synchronous Sequential Circuits Using Locally Available Lines [p 983]
- Reetz, R.
- Formal Specification in VHDL for Hardware Verification [p 257]
- Rencz, M.
- Fast Field Solvers for Thermal and Electrostatic Analysis [p 518]
- Renovell, M.
- RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
- Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]
- Ribas-Xirgo, L.
- On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits [p 624]
- Ricco, B.
- Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
- Richardson, A.M.D.
- Riesgo, T.
- Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
- Ringe, M.
- Path Verification Using Boolean Satisfiability [p 965]
- Robins, G.
- Improved Approximation Bounds for the Group Steiner Problem [p 406]
- Rodríguez-Montanés, R.
- Estimation of the Defective I
_{DDQ}Caused by Shorts in Deep-Submicron CMOS ICs [p 490] - Roethig, W.
- Power and Timing Modeling for ASIC Designs [p 969]
- Rosenberger, R.
- A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks [p 721]
- Rosenstiel, W.
- A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment [p 226]
- Formal Verification: A New Standard CAD Tool for the Industrial Design Flow [p 422]
- Verification by Simulation Comparison Using Interface Synthesis [p 436]
- Cross-Level Hierarchical High-Level Synthesis [p 451]
- Next Generation System Level Design Tools [p 488]
- A Comparing Study of Technology Mapping for FPGA [p 939]
- Rouzeyre, B.
- Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
- Roy, S.
- PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
- Rozon, C.
- VHDL Modelling and Analysis of Fault Secure Systems [p 148]
- Rudnick, E.M.
- Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
- Rueda, A.
- Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
- Runje, D.
- Universal Strong Encryption FPGA Core Implementation [p 923]
- Rutten, J.W.J.M.
- An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]

- Sakallah, K.A.
- AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
- Salapura, V.
- Hardware/Software Co-Design of a Fuzzy RISC Processor [p 875]
- Salice, F.
- A Model for System-Level Timed Analysis and Profiling [p 204]
- Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
- Salvi, D.
- Novel Technique for Testing FPGAs [p 89]
- Sami, M.
- A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
- Sánchez-Solano, S.
- XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
- Sansen, W.
- Sapatnekar, S.S.
- Efficient Minarea Retiming of Large Level-Clocked Circuits [p 840]
- Sarmiento, R.
- A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
- Sarto, E.
- Interconnect Tuning Strategies for High-Performance ICs [p 471]
- Sawada, H.
- Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
- Scheible, J.
- An Interactive Router for Analog IC Design [p 414]
- Schietke, J.
- Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset [p 325]
- Schmerler, S.
- Advanced Optimistic Approaches in Logic Simulation [p 362]
- Schneider, C.
- Schneider, K.
- Formal Specification in VHDL for Hardware Verification [p 257]
- Scholl, C.
- Multi-Output Functional Decomposition with Exploitation of Don't Cares [p 743]
- Schulze, S.
- An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
- Schumacher, G.
- Object-Oriented Modelling of Parallel Hardware Systems [p 234]
- Schwarz, P.
- A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
- Sciuto, D.
- A Model for System-Level Timed Analysis and Profiling [p 204]
- Power Estimation of Behavioral Descriptions [p 762]
- Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
- Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
- Sechi, G.
- Novel Technique for Testing FPGAs [p 89]
- Sedlmeier, A.
- PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]
- Shao, J.
- MCM Interconnect Design Using Two-Pole Approximation [p 544]
- Sharma, R.
- Interconnect Tuning Strategies for High-Performance ICs [p 471]
- Shen, Z.
- An Effective General Connectivity Concept for Clustering [p 398]
- Shi, C.-J.R.
- Efficient DC Fault Simulation of Nonlinear Analog Circuits [p 899]
- Shields Neely, W.
- Reconfigurable Logic for Systems on a Chip [p 340]
- Shirakawa, K.
- Innovative System-Level Design Environment Based on FORM for Transport Processing System [p 883]
- Silvano, C.
- Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
- Silveira, L.M.
- An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
- Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
- Simon, P.
- Design-Manufacturing Interface: Part II -- Applications [p 557]
- Song, J.
- An Effective General Connectivity Concept for Clustering [p 398]
- Sonza Reorda, M.
- Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
- Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
- Srinivasan, V.
- Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
- Stenz, G.
- Technology Mapping for Minimizing Gate and Routing Area [p 664]
- Straka, B.
- A Fully Digital Controlled Off-Chip I
_{DDQ}Measurement Unit [p 495] - IOCIMU -- An Integrated Off-Chip I
_{DDQ}Measurement Unit [p 959] - Strik, M.
- A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
- Sung, W.
- Optimized Timed Hardware Software Cosimulation without Roll-Back [p 945]
- Svajda, M.
- A Fully Digital Controlled Off-Chip I
_{DDQ}Measurement Unit [p 495] - IOCIMU -- An Integrated Off-Chip I
_{DDQ}Measurement Unit [p 959] - Székely, V.
- Fast Field Solvers for Thermal and Electrostatic Analysis [p 518]

- Tan, S.-Y.
- The Design of an Asynchronous VHDL Synthesizer [p 44]
- Tanurhan, Y.
- Advanced Optimistic Approaches in Logic Simulation [p 362]
- Thole, M.
- EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
- Tian, M.W.
- Efficient DC Fault Simulation of Nonlinear Analog Circuits [p 899]
- Timmer, A.H.
- Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
- A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
- Tlili, I.B.S.
- March Tests for Word-Oriented Memories [p 501]
- Tomiyama, H.
- Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
- Torroja, Y.
- Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
- Treytnar, D.
- Core Interconnect Testing Hazards [p 953]
- Tsanakas, P.
- AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]

- Uceda, J.
- Urriza, I.

- van de Goor, A.J.
- March Tests for Word-Oriented Memories [p 501]
- van Eijk, C.A.J.
- Sequential Equivalence Checking without State Space Traversal [p 618]
- An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
- van Meerbergen, J.L.
- Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
- A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
- Vandenbussche, J.
- Vanneuville, J.
- A Fully Digital Controlled Off-Chip I
_{DDQ}Measurement Unit [p 495] - Vázquez, D.
- Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
- Veith, C.
- PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]
- Velasco-Medina, J.
- Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
- Vemuri, R.
- Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
- Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures [p 389]
- Vercauteren, S.
- Efficient Verification Using Generalized Partial Order Analysis [p 782]
- Verkest, D.
- Efficient Verification Using Generalized Partial Order Analysis [p 782]
- Vietti, R.
- Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
- Vijayan, G.
- CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
- Violante, M.
- Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
- Vogels, T.J.
- Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
- Völkel, H.
- A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor [p 937]
- Volpe, L.
- Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
- Vrudhula, S.B.K.
- Data Driven Power Optimization of Sequential Circuits [p 686]
- Vygen, J.
- Algorithms for Detailed Placement of Standard Cells [p 321]

- Wahl, M.
- A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
- A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor [p 937]
- Waldschmidt, K.
- Repartitioning and Technology Mapping of Electronic Hybrid Systems [p 52]
- Wan, M.
- An Energy-Conscious Exploration Methodology for Reconfigurable DSPs [p 341]
- Wang, D.
- A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction [p 466]
- Wang, L.-C.
- Measuring the Effectiveness of Various Design Validation Approaches for PowerPC
^{TM}Microprocessor Arrays [p 273] - Wang, Q.
- Data Driven Power Optimization of Sequential Circuits [p 686]
- Wehn, N.
- Embedded DRAM Architectural Trade-Offs [p 704]
- White, J.
- Whittemore, J.P.
- AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
- Wilkinson, T.D.
- Willems, M.
- FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
- Williams, T.W.
- Core Interconnect Testing Hazards [p 953]
- Wolf, M.
- Automatic Topology Optimization for Analog Module Generators [p 961]
- Wong, D.F.
- A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing [p 479]
- Wunderlich, H.-J.
- Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
- Wünsche, S.
- A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]

- Yamashita, S.
- Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
- Yang, T.
- An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis [p 74]
- Yarmolik, V.N.
- Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
- Yasuura, H.
- Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
- Yeh, C.-W.
- On Removing Multiple Redundancies in Combinational Circuits [p 738]
- Yen, W.-F.
- The Design of an Asynchronous VHDL Synthesizer [p 44]
- Yi, J.-H.
- Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
- Yu, T.C.B.

- Zarkesh, A.M.
- Power and Timing Modeling for ASIC Designs [p 969]
- Zelikovsky, A.
- Improved Approximation Bounds for the Group Steiner Problem [p 406]
- Zeng, J.
- Measuring the Effectiveness of Various Design Validation Approaches for PowerPC
^{TM}Microprocessor Arrays [p 273] - Zhao, W.
- Testing DSP Cores Based on Self-Test Programs [p 166]
- Zhuang, W.
- An Effective General Connectivity Concept for Clustering [p 398]
- Zorian, Y.
- RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
- Built-In Self-Test with an Alternating Output [p 180]