New for DATE 2010 – Tool Seminars
DATE introduces the new tool seminar track. The track has half day presentation slots.
Please see below for details of participating companies at DATE 2010.
Title | Date | Time | Location | Logo |
|---|---|---|---|---|
| Enhancing Verification Efficiency Using Virtualization | Wed, 2010-03-10 | 09:00 - 13:00 | Seminar room 3 |  |
| SysML for HW/SW Co-design using Artisan Studio® including SystemC code generation and Co-Simulation using Atego Ace® | Wed, 2010-03-10 | 13:30 - 16:30 | Seminar room 3 |  |
| Chip-Package-System Co-analysis Methodology | Thu, 2010-03-11 | 09:00 - 13:00 | Seminar room 3 |  |
| Mentor’s Full Analog/Mixed Signal IC Design Flow | Thu, 2010-03-11 | 13:30 - 17:30 | Seminar room 3 |  |
