ENOSYS (intEgrated modelliNg and synthesis tOol flow for embedded SYStems design)

ENOSYS (intEgrated modelliNg and synthesis tOol flow for embedded SYStems design) (Booth: EP5)

Contact: Alec Vogt


ENOSYS (intEgrated modelliNg and synthesis tOol flow for embedded SYStems design)
Charwood Building, Holywell Park, Ashby Road, Loughborough, LE11 3AQ,
Germany

Tel: +44 1509227131
Fax: +44 (0)1509 276263

ENOSYS (intEgrated modelliNg and synthesis tOol flow for embedded SYStems design

E-Mail: alec.vogt@enosys-project.eu
Website: https://sites.google.com/a/enosys-project.eu/www/home

ENOSYS (intEgrated modelliNg and synthesis tOol flow for embedded SYStems design) is an FP7 research project developing a complete model-driven design flow for embedded systems design using a standard modelling language (UML-MARTE) and behavioural synthesis for hardware-software co-design and hardware synthesis. The methodology includes the ENOSYS modelling language based on UML-MARTE; automatic exploration of the hardware/software design space; synthesis of efficient descriptions for both the hardware (synthesizable HDL) and embedded software (C/C++) components; and targets a high-performance SoC platform (FPGA) which includes a multi-core extensible VLIW processor. The ENOSYS design flow is based on existing tools (Modelio for UML modeling and FalconML for behavioral synthesis) and novel research from the university partners. Validation of the design flow is being completed with case studies from the communications and multimedia markets. The project partners are: Softeam, Thales Communications and Security (France); University of Peloponnese, Intracom (Greece); Loughborough University, Axilica (UK)