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As technologies evolve to meet demands of higher performance, smaller size and lower cost, there are several challenges in the design of chip, package, and board which must be addressed with an integrated analysis and verification methodology. Maintaining global power integrity requires a solution that considers the entire power delivery from voltage regulator on the PCB to the transistor on the die. Meeting the stringent noise requirements of high-speed memory and serial interfaces require simultaneous consideration of the IO ring design, IO and decoupling capacitor placement, input switching pattern, and package/board power and signal layout. To ensure success, sufficient data sharing needs to occur between the IC, package, and system designers. It also requires an integrated tools and methodology with accurate modeling and the capacity to handle the whole system. This workshop will discuss the fundamentals of resonance and its impact on power delivery network noise, methods for suppressing noise and achieving target impedance, and modeling and analysis requirements for chip-package-system convergence. It will outline Apache’s solutions for various applications such as early package planning, DDR jitter verification, and EMI/EMC validation, along with correlated results. Please register here.