Functional and clock related bugs are top two causes for chip respins. While simulation remains an important technology for functional verification, a methodology that depends on simulation alone to detect design errors has become insufficient. A trend has emerged to automate formal techniques and apply automatic formal verification solution to design & verification so as to catch most bugs in the early phase of the design flow. Solid block level design quality will not only simplify verification tasks later in the verification stage, but also shorten project cycle dramatically.

Our presentation will focus on Satris experience of using Real Intent’s automatic formal verification solutions in our design and verification flow to catch functional errors and design issues related to asynchronous clock domain crossings. Examples will be shown on the types of design bugs found. We will also highlight the importance of Real Intent’s innovative technologies in finding some unique and corner-case bugs which would be hard to find otherwise through simulation. By incorporating automatic formal analysis techniques in our methodology, Satris is able to detect bugs much easily and early in the verification cycle, thereby shortening the overall project cycle.