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Verification is known to strongly influence project efforts and timelines. And software has an increasing impact on project success. As a result, smart verification taking into account embedded software becomes more and more important. Using virtualization of embedded hardware, verification efficiency can be improved in two ways: bottom up, incrementally augmenting traditional RTL verification with virtualized transaction-level models of processors and peripherals, as well as top down, starting with virtual platforms originally intended for early pre-silicon software development. This workshop will address both concepts in detail, featuring examples and demonstrations. Participants will learn about the role of transaction level models, best practices of using virtualization, and selecting the right prototyping approach.

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