Henderson, Nevada – March 3, 2008 - Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the world-wide release of ALINTTM , a stand-alone Verilog design rule checker that complies with the second edition of the STARC “RTL Design ...

>> read more

HENDERSON, Nevada – February 25th, 2008 -- Aldec, Inc., announced today the release of Riviera-PRO 2008.02, a mixed language HDL simulator that now includes VHDL 2007, integrated SystemC 2.2 compiler and SystemVerilog DPI support. Riviera-PRO offers mixed language verification support for VHDL, ...

>> read more

For Immediate Release

First product to support at-speed timing closure analysis, RTL testability improvement and fault coverage estimation for transition delay testing

MUNICH, Germany, March 10, 2008— Atrenta Inc., the leading provider of Early Design Closure® solutions to ...

>> read more

Q-STAR TEST AND SOURCEIII ANNOUNCE A STRATEGIC PARTNERSHIP TO HELP FURTHER REDUCE TEST COSTS AND ENHANCE PRODUCT QUALITY

Brugge, Belgium / El Dorado Hills, CA, USA — February 22, 2008 — Q-Star Test nv., the premier supplier of advanced high speed and high accurate IDD test and ...

>> read more

COFLUENT STUDIO ADDS ADVANCED MODELING CAPABILITIES FOR TELECOMMUNICATIONS AND NETWORKING SYSTEMS

Support for Dynamic Function Management Modeling

Targets Next-Generation Wireless Applications Such as Software-Defined Radio

NANTES, France – FEBRUARY 26, ...

>> read more

SANTA CLARA, Calif. –– March 6, 2008 –– EVE, the leader in hardware/software co-verification, today introduced ZeBu-Personal for system-on-chip (SoC) hardware verification and software development during Design Automation & Test in Europe (DATE) at ICM in Munich, Germany.

ZeBu-Personal, ...

>> read more

STMicroelectronics expands Certitude deployment worldwide through multi-year agreement

CAMPBELL, Calif. – March 5, 2008 – Certess, Inc. the provider of functional qualification tools for systems on a chip (SoCs) and intellectual property (IP) blocks, today announced that ...

>> read more

Micrologic Design Automation, Inc., a leading provider of EDA (Electronic Design Automation) solutions for nanometer IC design, today announced the production release of nanoRVInteractive™, Interactive Reliability-Aware design environment for custom and semi-custom IC’s layout. ...

>> read more

Verific Design Automation, best known for its Verilog, SystemVerilog and VHDL parsers and elaborators, said that its Netlist Only Parser is gaining momentum among electronic design automation (EDA) applications, especially from startup and emerging companies.

Verific's Netlist Only ...

>> read more

First Platform to Combine Full-Chip, Mixed-Signal Design, Analysis and Verification; Unequaled integration and automation of simulation, analog optimization, chip finishing and physical verification

SAN JOSE, Calif., Feb. 27, 2008 – Magma® Design Automation Inc. (Nasdaq: LAVA), a provider ...

>> read more