The first edition of our new DATE08 Previews service for preparing your DATE visit featured Automotive and can be downloaded from the DATE website. This second preview highlights DATE08's sessions covering physical design, manufacturing test and reliability of complex nano-chips.
Designing complex nano-chips is a challenging job, but putting these chips into cost-competitive, high volume production is just as challenging. The chips are required to function reliably throughout the application lifecycle - whether in cost sensitive consumer applications, safety critical automotive and aviation applications, or health critical life science applications. The continued commercial success of the semiconductor industry depends upon it meeting the demanding cost and reliability requirements of these high growth applications. And technology from the nanoelectronics design ecosystem is essential to meet these requirements.
DATE08's programme covers the latest research and development efforts in the field, including 20 sessions, 5
tutorials and 1 workshop. We are sure that this will be a week of informative presentations and enlightening
discussions, and we hope that this preview will help you to prepare your visit to DATE. Finally, we would like to
invite you to help us to improve.
Please send your feedback to: datepreviews@edacentrum.de.
Donatella Sciuto, General Chair DATE08
Juergen Haase, Publicity Chair
| Abstract | Programme Excerpt |
Guest Comment |
Person Index |
News & Background |
DATE in the News |
DATE Links |
Programme Excerpt (Highlights)Tuesday, 3/11/2008 14:30-16:00, Room 05 2.1 From IDM to “Fab-Lite”: What Changes in your EDA Strategy? (Executive Session) Wednesday, 3/12/2008 8:30-10:00, Room 12 4.7 Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm (Panel Session) Thursday, 3/13/2008 16:00-17:30, Room 13a
11.7 3D Integration or How to Scale in the 21st Century |
AbstractThe manufacturability of reliable systems with an acceptable yield is a key challenge for both IDMs and silicon foundries. And, as we progress further into the nanoelectronic age, chip designers must increasingly comprehend manufacturability and reliability in their design flows. The following DATE sessions cover the most important manufacturability and reliability issues: Monday’s tutorials cover physical design, manufacturing test and reliability, presenting new methodologies ... | ||
Person Index (Highlights)Rudy Lauwereins, IMEC, BE 3.1 The Perils of 45nm: A Report on the Move Tuesday, March 11 16:30-18:00, Room 05 (Executive) 4.7 Caution Ahead: The Road to Design and Manufacturing at 32 Wednesday, March 12 8:30-10:00, Room 12 (Panelist) Philippe Magarshack, STMicroelectronics, FR 2.1 From IDM to "Fab-Lite": What Changes in your EDA Strategy? Tuesday, March 11 14:30-16:00, Room 05 (Executive) E J Marinissen, NXP Semiconductors, NL 2.5 Advances in SOC Test Tuesday, March 11 14:30-16:00, Room 11 (Speaker) 10.5 A Smorgardsbord of Test Thursday, March 13 14:00-15:30, Room 11 (Moderator) Volker Kiefer, Qimonda, DE 4.7 Caution Ahead: The Road to Design and Manufacturing at 32 Wednesday, March 12 8:30-10:00, Room 12 (Panelist) T W Williams, Synopsys, US 3.1 The Perils of 45nm: A Report on the Move Tuesday, March 11 16:30-18:00, Room 05 (Moderator) ... Read more | Guest Comment
Juergen Schloeffel, NXP Semiconductors Germany GmbH, Principal, Project Manager, Corp. I&T / Design Technology & Flows Yes, DFX is still the key! What is the "X" factor? Is it Test or Reliability or Manufacturability or Yield? - It's all of these. We need sophisticated design methodologies and technologies that comprehend the "X" factor to realize the reliable systems and chips of the future. We have to take up-front measures to make it even possible to manufacture such highly integrated circuits. We have to design quality into the products before we ship them to the customer. And, to achieve this, we must treat chip design as a closed loop through the system architecture, ... | ||
News & BackgroundIndustry collaboration is tackling IC yield issues EETimes, January 07, 2008 ATopTech, a new face in physical design EETimes, December 10, 2007 ... Read more | DATE in the NewsKeynote Events in the DATE'08 Conference Programme Embedded Computing Design, December 12,2007 ... Read more | DATE LinksDATE in the web:
... Read more |
The manufacturability of reliable systems with an acceptable yield is a key challenge for both IDMs and silicon foundries. And, as we progress further into the nanoelectronic age, chip designers must increasingly comprehend manufacturability and reliability in their design flows. The following DATE sessions cover the most important manufacturability and reliability issues:
Monday’s tutorials cover physical design, manufacturing test and reliability, presenting new methodologies and solutions for design variability, power gating for ultra low leakage, power aware testing, design for manufacturing (DfM) in the analog and digital worlds, and soft errors.
Tuesday’s highlight session "From IDM to Fab-Lite: What Changes in your EDA Strategy?" discusses the implications of integrated device manufacturers (IDM) and third party fab alliances on semiconductor technology, libraries and EDA flows. The day commences with sessions covering 45 nm, adoption status and issues , the road to 22 nm, mixed-signal BIST, and continues with sessions covering SOC test and fault tolerant techniques.
On Wednesday, the sessions commence with DFX and statistical physical defect testing, continuing with robust mixed-signal system design, test challenges for low power devices, pin-to-transistor physical design and design techniques for error mitigation.On Thursday, the morning sessions cover power aware circuit and process techniques, test generation for new technologies, the smorgardsbord of test, nanometer analog design, and 3D integration to scale in the 21st century.
Friday will close the week with a workshop about the impact of process variability on design and test.
Juergen Schloeffel, NXP Semiconductors Germany GmbH, Principal, Project Manager, Corp. I&T / Design Technology & Flows
Juergen Schloeffel was born in Kassel, Germany on September 7, 1957. He studied Physics at the University of Goettingen where he received the Diploma in 1986. After different functions on characterization, library development and CAD he today is a Project Manager and Principal in the field of EDA and DfT, including the development of new tools and methods for automated test and diagnosis solutions.
Yes, DFX is still the key! What is the "X" factor? Is it Test or Reliability or Manufacturability or Yield? - It's all of these. We need sophisticated design methodologies and technologies that comprehend the "X" factor to realize the reliable systems and chips of the future. We have to take up-front measures to make it even possible to manufacture such highly integrated circuits. We have to design quality into the products before we ship them to the customer. And, to achieve this, we must treat chip design as a closed loop through the system architecture, functional and physical design, and manufacturing and test, rather than as a linear flow.
The DATE08 program is a primary forum for discussing these sophisticated "X" factor methodologies and technologies. For instance, yield is a major challenge that IDM and foundries face in migrating to the latest manufacturing process technologies. So yield enhancement methodologies and design technologies are a hot topic, along with other approaches that can reduce test and manufacturing costs. They will be discussed on conferences like DATE. One successful example of these discussions is test data compression, which is now an accepted methodology. The question in many prior conferences used to be "should we use test compression?" Today, the question is "why are there designers who still don't use it?" But there is still a lot to do, and R&D is ongoing.
Another interesting upcoming approach are fault tolerant designs. What will change is that we will not only strive to find each and every possible failure, but also learn to work with architectures and design approaches that can tolerate or cope with specific fault behaviors.
And how far can we go with statistical approaches to test integrated hardware? Also, "low power" continues to be a hot topic at design conferences. What are the challenges in testing such low power designs - and what about the implications of power consumption during test?
Besides these looming challenges, we also face old challenges, but in new areas. Radiation-induced soft errors have been with us for decades, but will become more and more an issue in future technology nodes following the ongoing trend of miniaturization.
The DATE08 program addresses all of these issues - and more. That's why the DATE is Europe's largest design conference. Can you really afford to miss it?
DATE has focused on test and reliability issues for several years. And each DATE reveals a variety of new approaches and possible solutions. This year will be no different. Physical design, test and reliability are the subjects of a lot of tutorials, contributions and hot-topic sessions. And, as in the past, these will be the basis for fruitful discussions between chip companies, EDA companies and academia.
I'm looking forward to an interesting event! See you at DATE08.
9:30-13:00, Room 11b
Driven by aggressive technology scaling and sub-wavelength lithography, there has been a marked increase in the variability of process technology parameters. In addition, due to increased power density and stricter thermal envelopes, environmental parameter variability (e.g., temperature and voltage variation) increases as well. While a significant body of work exists for characterizing performance and power consumption in the presence of process-driven variability at the interface between physical-gate levels, these effects need to be modeled at higher levels of abstraction as well. Current high-level design methodologies targeting architecture and system levels still assume a classic static timing behavior and do not include effects of variability on performance or energy. In support of a complete probabilistic design flow, high-level modeling of variability effects is needed for determining design choices that are most likely to meet initial design constraints. This objective becomes even more important in the case of complex multi-core designs that are unable to be analyzed by existing variability-aware tools. ... Read more
9:30-13:00, Room 04a
The demand for portable electronic devices continues to grow rapidly and has generated great interest in low power design, which initially focused on controlling dynamic power consumption. However, the combination of wireless device operational characteristics and exponentially increasing leakage power in new processes motivated the development of leakage reduction techniques. ... Read more
9:30-13:00, Room 12a
Power dissipation has become a major design objective in many application areas. At the same time, it is also becoming a critical parameter during manufacturing test, as the design can consume much more power than during functional mode of operation. This tutorial discusses issues arising from excessive power consumption during test application and provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems. The first part of the tutorial will provide necessary background on power and energy modeling. Then, motivations for reducing power during test will be discussed and examples of issues raised by excessive test power will be given. The remaining parts will present state-of-the-art low-power test techniques to deal with nanometer designs. Techniques ... Read more
14:30-18:00, Room 04a
No matter whether the designer thinks analog or digital, he is faced with the DfM issue. Although confronted with different challenges, the key for satisfying yield in production lies in the design phase. Tools, techniques, and methods that once worked without fail cannot hold up any longer. More of the responsibility for yield must shift to the designer, so the fabless model, where foundry information flows freely, increases in importance. ... Read more
14:30-18:00, Room 12a
Radiation-induced soft errors are getting worse in digital systems manufactured in advanced technologies. Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors in sequential elements and combinational logic. This tutorial will discuss the impact of technology scaling on soft error rates, system effects of soft errors, actual data on system behaviors in the presence of soft errors from latest systems, CAD techniques for quantifying soft error vulnerabilities, design of architectures with Built-in-Soft-Error-Resilience techniques, and actual case studies of protection techniques. ... Read more
11:30-13:00, Room 11
In this session, several BIST solutions for MS devices are presented. First, the Goetzel algorithm is used for test data evaluation. Next, a multivariate kernel estimator is used to estimate non-normality of performance densities to set BIST limits. Then, a new diagnostic analysis for ADCs is proposed using DfT structures. Finally, an implementation of a network analyzer for evaluation purposes on a test board is presented. ... Read more
14:30-16:00, Room 05
Significant announcements were made in the last 18 months by integrated design manufacturers (IDMs) such as ST, NXP, TI, on changing their semiconductor developments plans for 32nm to rely much more strongly on alliances of companies to share resources. As these plans firm up, there will be implications on a number of aspects of their EDA strategies. The participants will focus on these changes and the opportunities they present. Will there be much more commonality and sharing in design libraries? Or design flows? Will there be more EDA tool standardisation among members of the same technology consortiums? ... Read more
14:30-16:00, Room 04a
This session addresses several topics of automotive system design including network reliability and temporal behaviour verification. Electro magnetic compatibility optimization and a new driver assistance application are also presented. ... Read more
14:30-16:00, Room 11
Increasing test data volumes are major problems for SOCs. This session addresses modular testing, test data compression, and low cost testers for SOC testing. ... Read more
16:30-18:00, Room 05
The industry move towards design and the production ramp up of 45nm technologies continues to make progress. But contrasted to the predictions of only a few years ago, how is the move really going? Issues were raised about the need for new design techniques, such as the use of statistical methods and increased manufacturing concerns in order to achieve yields. Some effects would become much more pronounced, such as leakage. All this in addition to the general problem of the increased cost of design as complexity would certainly be larger. The panellists will cover some of their experiences as their companies are undergoing this change, and highlight new concerns based on what they have been able to observe so far. ... Read more
16:30-18:00, Room 11
Soft errors are claimed to likely affect the correct behavior of deep-sub-micron technologies also at the sea level. This session deals with methods aiming to achieve tolerance toward faults either of transient or permanent nature. The proposed papers will drive the audience across different perspectives and solutions for fault tolerance. ... Read more
8:30-10:00, Room 11
This session covers recent advances on design techniques for reducing test and manufacturing cost. Topics include an innovative technique for low-power scan testing, scan-chain partitioning for logic diagnosis, test compression, and yield enhancement for regular fabrics composed of logic bricks. ... Read more
8:30-10:00, Room 12
At 32 and 22 nm, which manufacturing technology changes will be so revolutionary as to cause upheavals in the semiconductor supply chain and on design practices? •Will there be economic fallout from the higher mask cost associated with dual patterning? How will designers deal with place-and-route restrictions? •How likely is “direct write”? What design and OPC tool changes will be required? •When dealing with stress and CMP, will we need to replace DRC with a new breed of tools? •How will designers “sign off” on a design at 32 nm? These are just some of the challenges ahead. For every solution, collateral adjustments must be made to design technologies and methodologies. Everyone from designer to foundry equipment manufacturer would do well to look ahead at these potential hazards on the road to 32 and 22 nm. ... Read more
11:00-12:30, Room 11
This session is focused on various aspect of physical and statistical testing. The papers (i) report results from case study of lithography related open faults focusing on the test design aspects, (ii) introduce a method for optimal determination of test margins for at-speed testing which minimises the yield loss (iii) demonstrate the applicability of an interactive resistive bridging fault simulator to large industrial circuits and (iv) describe a test selection approach for generating compact N-defect test sets based on physically aware metrics. ... Read more
14:30-16:00, Room 05
Time predictability is related to the capability of predicting the system-level timing behaviour (latencies and jitter), resulting from the synchronisation between tasks and messages, but also from the synchronisation and queuing policies of the middleware and RTOS levels. In this session, we review tools for the evaluation by simulation or by static analysis of timing properties of complex embedded systems. ... Read more
14:30-16:00, Room 03
The challenges in modern deep submicron CMOS design include stringent requirements such as very low supply voltages, process variations and large device mismatches. This session presents four papers which discuss novel mixed-signal circuit and system design techniques to cope with these challenges: low-voltage design styles, temperature compensation, offset cancellation, and finally the upcoming topic of energy harvesting circuits. ... Read more
14:30-16:00, Room 11
Elaborate power management strategies, like dynamic voltage or frequency scaling, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. First, the session discusses the power issues raised during manufacturing test. Next, it visits some key aspects of test challenges for low power devices, and shows how these devices can be tested safely without affecting yield and reliability. Finally, it shows how existing EDA tools can handle such issues and what could be done to improve these tools. ... Read more
16:30-18:00, Room 03
This session offers a rich selection of hot topics in physical design. The results reported here break new ground on pin assignment, library cell development, timing optimization and DFM. ... Read more
16:30-18:00, Room 11
This session proposes cost effective techniques for the mitigation of error effects in the emerging technologies. These problems are addressed at different abstraction levels, from gate level up to the system architecture. Concurrent techniques are exploited as well. ... Read more
8:30-10:00, Room 03
The first two papers in this session address process variation and noise effects which represent an increasing concern in upcoming technology nodes. It is followed by two innovative papers on circuit techniques for level shifting and clock distribution. ... Read more
11:00-12:30, Room 11
Fault models and test pattern generation tackling constraints and requirements for new design technologies are presented. At first, the relationship between bridging faults and logic redundancy is investigated, the next presentation deals with test pattern generation for transition faults taking into account layout considerations. Then multi-vector tests as a method for error-rate testing are considered. The session terminates with a paper using X-filling techniques to reduce power in scan-based testing. ... Read more
14:00-15:30, Room 11
The session presents a variety of test topics: automated trace signal identification, functional test of symmetric multiprocessors, and theoretical and practical aspects of IDDQ. ... Read more
16:00-17:30, Room 11
First, a jitter expansion technique is presented, allowing high- resolution jitter testing of high-speed digital signals at low cost. Next, a new type of fault dictionary with improved diagnostic resolution is introduced. Then, a technique is introduced for delay adjustment of multi-gigahertz signals on a picosecond scale without distortion. Finally, a low cost Design-for-Diagnosis technique for embedded SRAMs is presented. ... Read more
16:00-17:30, Room 13a
3D integration offers numerous opportunities for design, and is probably the best hope for carrying ICs along (and even beyond) the path of Moore’s Law in the 21st century. However, many questions still need to be answered to take advantage of 3D. First, what will become the mainstream 3D technology? Today, many technology options are proposed, but each having different cost, design and test implications. Secondly, how to make 3D designs reliable? Many unknowns still exist related to thermal load, reliability and signal integrity challenges. Finally, what about design solutions/methods and architectural modifications for 3D integration? The objective of this special session is to create a better understanding of forthcoming 3D technologies, their implication on design and test. An attempt will be made to roadmap 3D technologies and their design implications. This will enable R&D planning by design houses, EDA vendors, foundries and academia, paving the way for a widespread acceptance of 3D technologies. ... Read more
8:30-16:40, Room 04a
Integrated circuit technology continues to shrink. Mainstream semiconductors are starting to be produced at the 45nm technology node, where transistors and wires measure less than 100 atoms across. The discrepancies between lithography wavelengths and circuit feature sizes increase. Lower power supply levels and increasing operating speeds significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is increasingly difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Process variation cannot be solved by improving manufacturing tolerances. Variability must be reduced by new device technology or managed by design in order for scaling to continue. Within-die performance variation also imposes new challenges for test methods. Test hardware must be embedded in the design to detect errors dynamically, isolate and confine faults, reconfigure the system to work around faults using spare hardware, and recover from errors on the fly. This will become increasingly important as devices experience parametric degradation over time, requiring run-time reconfiguration. This workshop will provide a forum for researchers from industry and academia where the latest results can be presented and ideas exchanged between those working on different approaches to dealing with variability. The scope of this workshop covers all aspects of process variation. At the transistor level, this includes new devices to replace CMOS in order to reduce variability, and the modelling of transistor devices at atomic scales so variation can be understood. From the viewpoint of fabrication technology, new techniques and CAD tools for predicting and compensating for the effect of variability in processes are of interest. At the circuit and system level, tools and design methods must be aware of variation, without adding extra complexity that renders design intractable. Process variation-aware test and reliability methods together with various design techniques that allow circuits and systems to adapt variability are also of particular relevance. By bringing together researchers from different areas of expertise, this workshop aims to encourage collaborative research that tackles the problems of process variation from several levels simultaneously. ... Read more
N Alt, TU Munich, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Speaker)
L Anghel, TIMA Laboratory, FR
3.5 Fault Tolerant Techniques
Tuesday, March 11 16:30-18:00, Room 11 (Moderator)
D Appello, STMicroelectronics, IT
3.5 Fault Tolerant Techniques
Tuesday, March 11 16:30-18:00, Room 11 (Moderator)
Petru Bacinschi, TU Darmstadt, DE
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Speaker)
Luca Benini, Bologna U, IT
11.7 3D Integration or How to Scale in the 21st Century
Thursday, March 13 16:00-17:30, Room 13a (Presenter)
8.3 Power-Aware Circuit and Process Techniques
Thursday, March 13 8:30-10:00, Room 03 (Speaker, Speaker)
Mladen Berekovic, TU Braunschweig, DE
W2 Impact of Process Variability on Design and Test
Friday, March 14 8:30-16:40, Room 04a (Organizer)
Emmanuel Blanc, Mentor Graphics, FR
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Speaker)
Ivo Bolsens, Xilinx, US
2.1 From IDM to "Fab-Lite: What Changes in your EDA Strategy?
Tuesday, March 11 14:30-16:00, Room 05 (Executive)
Bruno Bougard, IMEC, BE
11.7 3D Integration or How to Scale in the 21st Century
Thursday, March 13 16:00-17:30, Room 13a (Organizer)
Krishendu Chakrabarty, Duke University, US
2.5 Advances in SOC Test
Tuesday, March 11 14:30-16:00, Room 11 (Speaker)
Peter Y.K. Cheung, Imperial College London, UK
W2 Impact of Process Variability on Design and Test
Friday, March 14 8:30-16:40, Room 04a (Speaker)
John Chilton, Synopsys, US
2.1 From IDM to "Fab-Lite": What Changes in your EDA Strategy?
Tuesday, March 11 14:30-16:00, Room 05 (Executive)
C Claus, TU Munich, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Barry Dennington, NXP, UK
2.1 From IDM to "Fab-Lite": What Changes in your EDA Strategy?
Tuesday, March 11 14:30-16:00, Room 05 (Executive)
M Di Natale, Scuola S Anna Pisa, IT
6.1 Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures (Automotive Special Day)
Wednesday, March 12 14:30-16:00, Room 05 (Organizer, Moderator)
A Doboli, State U of New York at Stony Brook, US
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Moderator)
Antun Domic, Synopsys, US
2.1 From IDM to "Fab-Lite": What Changes in your EDA Strategy?
Tuesday, March 11 14:30-16:00, Room 05 (Organizer)
3.1 The Perils of 45nm: A Report on the Move
Tuesday, March 11 16:30-18:00, Room 05 (Organizer)
Carsten Elgert, Mentor Graphics, DE
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Organizer)
Rolf Ernst, TU Braunschweig, DE
6.1 Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures (Automotive Special Day)
Wednesday, March 12 14:30-16:00, Room 05 (Presenter)
Luca Fanucci, Pisa U, IT
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Moderator)
Elof Frank, VAST, DE
6.1 Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures (Automotive Special Day)
Wednesday, March 12 14:30-16:00, Room 05 (Presenter)
Jerry Frenkil, Sequence Design, US
E1 Power Gating for Ultra-low Leakage: Physics, Design and Analysis
Monday, March 10 9:30-13:00, Room 04a (Organizer, Speaker)
Robert Gardner, EDA Consortium, US
2.1 From IDM to "Fab-Lite": What Changes in your EDA Strategy?
Tuesday, March 11 14:30-16:00, Room 05 (Organizer)
3.1 The Perils of 45nm: A Report on the Move
Tuesday, March 11 16:30-18:00, Room 05 (Organizer)
Rajesh Garg, Texas A&M U, US
8.3 Power-Aware Circuit and Process Techniques
Thursday, March 13 8:30-10:00, Room 03 (Speaker)
Joachim Gerlach, Robert Bosch GmbH, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Moderator)
Jean-Pierre Geronimi, STMicroelectronics, FR
3.1 The Perils of 45nm: A Report on the Move
Tuesday, March 11 16:30-18:00, Room 05 (Executive)
Swaroop Ghosh, Purdue U, US
3.5 Fault Tolerant Techniques
Tuesday, March 11 16:30-18:00, Room 11 (Speaker)
Patrick Girard, LIRMM/CNRS, FR
6.5 Test Challenges for Low Power Devices
Wednesday, March 12 14:30-16:00, Room 11 (Organizer)
G1 Power-Aware Testing and Test Strategies for Low Power Devices
Monday, March 10 9:30-13:00, Room 12a (Speaker)
Dimitris Gizopoulos, Piraeus U, GR
G1 Power-Aware Testing and Test Strategies for Low Power Devices
Monday, March 10 9:30-13:00, Room 12a (Organizer)
G2 Soft Errors: System Effects, Protection Techniques and Case Studies
Monday, March 10 14:30-18:00, Room 12a (Organizer)
M Glass, Erlangen-Nuernberg U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Speaker)
Thomas Harms, Infineon, DE
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Speaker)
P Harrod, ARM, UK
2.5 Advances in SOC Test
Tuesday, March 11 14:30-16:00, Room 11 (Moderator)
Christian Haubelt, Erlangen-Nuremberg U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Joerg Henkel, Karlsruhe U, DE
8.3 Power-Aware Circuit and Process Techniques
Thursday, March 13 8:30-10:00, Room 03 (Moderator)
M Hirech, Synopsys, US
6.5 Test Challenges for Low Power Devices
Wednesday, March 12 14:30-16:00, Room 11 (Presenter)
E. Hoene, Fraunhofer Inst. For Reliability and Microintegration, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Speaker)
A Jain, Cavium Networks, US
3.1 The Perils of 45nm: A Report on the Move
Tuesday, March 11 16:30-18:00, Room 05 (Executive)
Roy Kaushik, Purdue U, US
G1 Power-Aware Testing and Test Strategies for Low Power Devices
Monday, March 10 9:30-13:00, Room 12a (Organizer)
G2 Soft Errors: System Effects, Protection Techniques and Case Studies
Monday, March 10 14:30-18:00, Room 12a (Organizer)
Doris Keitel-Schulz, Qimonda, DE
11.7 3D Integration or How to Scale in the 21st Century
Thursday, March 13 16:00-17:30, Room 13a (Presenter)
H.G. Kerkhoff, Twente U, NL
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Moderator)
Volker Kiefer, Qimonda, DE
4.7 Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm
Wednesday, March 12 8:30-10:00, Room 12 (Panelist)
T Kirsten, NEC Electronics (Europe) GmbH, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Speaker)
Thomas Kropf, Tuebingen U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Lucio L. Lanza, Lanza Ventures, US
2.1 From IDM to "Fab-Lite": What Changes in your EDA Strategy?
Tuesday, March 11 14:30-16:00, Room 05 (Executive)
Rudy Lauwereins, IMEC, BE
3.1 The Perils of 45nm: A Report on the Move
Tuesday, March 11 16:30-18:00, Room 05 (Executive)
4.7 Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm
Wednesday, March 12 8:30-10:00, Room 12 (Panelist)
Andreas Leininger, Infineon, DE
10.5 A Smorgardsbord of Test
Thursday, March 13 14:00-15:30, Room 11 (Moderator)
D Lettnin, Tuebingen U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Speaker)
Jens Lienig, TU Dresden, DE
7.3 Physical Design: From Pins to Transistors
Wednesday, March 12 16:30-18:00, Room 03 (Speaker)
A Lissner, Fraunhofer Inst. For Reliability and Microintegration, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
M Lukasiewycz, Erlangen-Nuernberg U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
J Machado Da Silva, INESC, PT
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Moderator)
Enrico Macii, Politecnico di Torino, IT
8.3 Power-Aware Circuit and Process Techniques
Thursday, March 13 8:30-10:00, Room 03 (Speaker)
Philippe Magarshack, STMicroelectronics, FR
2.1 From IDM to "Fab-Lite": What Changes in your EDA Strategy?
Tuesday, March 11 14:30-16:00, Room 05 (Executive)
Hans Manhaeve, Qstart, BE
5.5 Statistical, Physical Defect Based Testing
Wednesday, March 12 11:00-12:30, Room 11 (Moderator)
Paul Marchalz, IMEC, BE
11.7 3D Integration or How to Scale in the 21st Century
Thursday, March 13 16:00-17:30, Room 13a (Organizer, Moderator)
Diana Marculescu, Carnegie Mellon U, US
D1 Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level
Monday, March 10 9:30-13:00, Room 11b (Speaker, Organizer)
E J Marinissen, NXP Semiconductors, NL
2.5 Advances in SOC Test
Tuesday, March 11 14:30-16:00, Room 11 (Speaker)
10.5 A Smorgardsbord of Test
Thursday, March 13 14:00-15:30, Room 11 (Moderator)
Igor L. Markov, U Michigan, US
7.3 Physical Design: From Pins to Transistors
Wednesday, March 12 16:30-18:00, Room 03 (Moderator)
Heinz Mattes, Infineon Technologies, DE
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Subhasish Mitra, Stanford U, US
G2 Soft Errors: System Effects, Protection Techniques and Case Studies
Monday, March 10 14:30-18:00, Room 12a (Speaker)
Pradeep K. Nalla, Tuebingen U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Sani Nassif, IBM, US
D1 Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level
Monday, March 10 9:30-13:00, Room 11b (Speaker)
W2 Impact of Process Variability on Design and Test
Friday, March 14 8:30-16:40, Room 04a (Speaker)
Nicola Nicolici, McMaster U, CA
G1 Power-Aware Testing and Test Strategies for Low Power Devices
Monday, March 10 9:30-13:00, Room 12a (Speaker)
Hermann Obermeir, Infineon, DE
9.5 Test Generation for New Technologies
Thursday, March 13 11:00-12:30, Room 11 (Moderator)
Yoshifumi Okamoto, Matsushita/Panasonic, JP
3.1 The Perils of 45nm: A Report on the Move
Tuesday, March 11 16:30-18:00, Room 05 (Executive)
Anton Ossner, Chartered Semiconductor, DE
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Speaker)
C Papachristou, Case Western Reserve U, US
7.5 Design Techniques for Error Mitigation
Wednesday, March 12 16:30-18:00, Room 11 (Moderator)
Antonis Paschalis, Athens U, GR
10.5 A Smorgardsbord of Test
Thursday, March 13 14:00-15:30, Room 11 (Speaker)
Jose Pineda de Gyvez, NXP Semiconductors Research and TU Eindhoven, NL
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Irith Pomeranz, Purdue U, US
11.5 Jitter Test and Fault Diagnosis
Thursday, March 13 16:00-17:30, Room 11 (Speaker)
9.5 Test Generation for New Technologies
Thursday, March 13 11:00-12:30, Room 11 (Speaker)
Dhiraj Pradhan, Bristol U, UK
7.5 Design Techniques for Error Mitigation
Wednesday, March 12 16:30-18:00, Room 11 (Moderator)
A Raghunathan, NEC Labs, US
6.5 Test Challenges for Low Power Devices
Wednesday, March 12 14:30-16:00, Room 11 (Moderator)
Wenjing Rao, UC San Diego, US
3.5 Fault Tolerant Techniques
Tuesday, March 11 16:30-18:00, Room 11 (Speaker)
C P Ravikumar, Texas Instruments, IN
6.5 Test Challenges for Low Power Devices
Wednesday, March 12 14:30-16:00, Room 11 (Presenter)
Sudhakar M. Reddy, Iowa U, US
11.5 Jitter Test and Fault Diagnosis
Thursday, March 13 16:00-17:30, Room 11 (Speaker)
F Reimann, Erlangen-Nuernberg U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
S Reitemeyer, NEC Electronics (Europe) GmbH, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Wolfgang Rosenstiel, Tuebingen U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Scott Roy, Glasgow U, UK
W2 Impact of Process Variability on Design and Test
Friday, March 14 8:30-16:40, Room 04a (Speaker)
Juergen Ruf, Tuebingen U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Pia Sanda, IBM, US
G2 Soft Errors: System Effects, Protection Techniques and Case Studies
Monday, March 10 14:30-18:00, Room 12a (Speaker)
Alberto L. Sangiovanni-Vincentelli, UC Berkeley, US
6.1 Methods, Tools and Standards for the Analysis and Evaluation of Modern Automotive Architectures (Automotive Special Day)
Wednesday, March 12 14:30-16:00, Room 05 (Organizer)
Sebastian Sattler, Infineon Technologies, DE
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Louis Scheffer, Cadence Design Systems, US
7.3 Physical Design: From Pins to Transistors
Wednesday, March 12 16:30-18:00, Room 03 (Moderator)
Juergen Schloeffel, NXP Semiconductors, DE
4.5 DFX: Support for Test, Manufacturing, and Diagnosis
Wednesday, March 12 8:30-10:00, Room 11 (Moderator)
V Schoenknecht, NEC Electronics (Europe) GmbH, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
B Schroeder, Mentor Graphics, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Pete Sedcole, Imperial College London, UK
W2 Impact of Process Variability on Design and Test
Friday, March 14 8:30-16:40, Room 04a (Organizer)
Jaume Segura, Balearic Islands U, ES
5.5 Statistical, Physical Defect Based Testing
Wednesday, March 12 11:00-12:30, Room 11 (Moderator)
Amith Singhee, Carnegie Mellon U, US
7.3 Physical Design: From Pins to Transistors
Wednesday, March 12 16:30-18:00, Room 03 (Speaker)
Brian D. Smith, Royal Institute of Technology, UK
8.3 Power-Aware Circuit and Process Techniques
Thursday, March 13 8:30-10:00, Room 03 (Moderator)
M Sonza Reorda, Politecnico di Torino, IT
11.5 Jitter Test and Fault Diagnosis
Thursday, March 13 16:00-17:30, Room 11 (Moderator)
Walter Stechele, TU Munich, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
B Stube, Mentor Graphics, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Speaker)
Juergen Teich, Erlangen-Nuremberg U, DE
2.4 Automotive System Design and Verification
Tuesday, March 11 14:30-16:00, Room 04a (Author)
Paolo J Teixeira, INESC, PT
9.5 Test Generation for New Technologies
Thursday, March 13 11:00-12:30, Room 11 (Moderator)
Sharon Turnoy, Synopsys, US
4.7 Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm
Wednesday, March 12 8:30-10:00, Room 12 (Organizer)
Ted Vucurevich, Cadence Design Systems, US
3.1 The Perils of 45nm: A Report on the Move
Tuesday, March 11 16:30-18:00, Room 05 (Executive)
Xiaoqing Wen, Kyushu Institute of Technology, JP
6.5 Test Challenges for Low Power Devices
Wednesday, March 12 14:30-16:00, Room 11 (Presenter)
G1 Power-Aware Testing and Test Strategies for Low Power Devices
Monday, March 10 9:30-13:00, Room 12a (Speaker)
T W Williams, Synopsys, US
3.1 The Perils of 45nm: A Report on the Move
Tuesday, March 11 16:30-18:00, Room 05 (Moderator)
Peter Wintermayr, Elektronik.net, DE
4.7 Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm
Wednesday, March 12 8:30-10:00, Room 12 (Moderator)
T Yoneda, Nara Inst. of Science and Technology, JP
4.5 DFX: Support for Test, Manufacturing, and Diagnosis
Wednesday, March 12 8:30-10:00, Room 11 (Moderator)
A Zjajo, NXP Semiconductors, NL
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
11.5 Jitter Test and Fault Diagnosis
Thursday, March 13 16:00-17:30, Room 11 (Moderator)
TTTC
The Test Technology Technical Committee
http://tab.computer.org/tttc
IC Physical Design Tools
List & Overview
http://ecat.edacafe.com/corplist.php?category_id=1000048&alpha=0-Z&cat_name=IC%20Physical%20Design%20Tools&explodeid=1000043
IC Test and Yield Learning Report
Newsletter about IC Test and Yield Learning
http://www.yieldlearning.com
3D IC Alliance
Consortium webpage of integrated circuit designers, developers, and manufacturers
http://3d-ic.org
3D IC Industry Summary
prepared by Tezzaron Semiconductor
http://www.tezzaron.com/technology/3D%20IC%20Summary.htm
Industry collaboration is tackling IC yield issues
EETimes, January 07, 2008
http://www.eetimes.com/showArticle.jhtml;jsessionid=MS0Q1ZSNMUCOUQSNDLPCKHSCJUNN2JVN?articleID=205207021
ATopTech, a new face in physical design
EETimes, December 10, 2007
http://www.eetimes.com/showArticle.jhtml;jsessionid=MS0Q1ZSNMUCOUQSNDLPCKHSCJUNN2JVN?articleID=204801075
IEDM examines the impact of electronic devices
EETimes, December 06, 2007
http://www.eetimes.com/showArticle.jhtml;jsessionid=MS0Q1ZSNMUCOUQSNDLPCKHSCJUNN2JVN?articleID=204701824
Keynote Events in the DATE'08 Conference Programme
Embedded Computing Design, December 12, 2007
http://www.embedded-computing.com/news/db/?9699
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Editorial Preview - Automotive Systems @ DATE’08
DATE, January 09,2008
http://www.date-conference.com/media/automotive_systems/date08_automotive_systems.html
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