Welcome to the 4th issue of the DATE08 Preview, which addresses electronic system level (ESL) design and embedded system design. Here, we provide a snapshot of the DATE08 program that covers these hot topics, plus Gary Smith’s analysis of the current situation, and additional news and background information.
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| Abstract | Programme Excerpt |
Guest Comment |
Person Index |
News & Background |
DATE in the News |
DATE Links |
Programme Excerpt (Highlights)Tuesday, 3/11/2008, 09:50-10:30, Room 13 Plenary: Perspective on Embedded Systems: Challenges and Research Priorities (Keynote) Tuesday, 3/11/2008, 11:30-13:00, Room 05 1.1 Unifying or Overrated: A System Level Design Strategy (Executive Session) Tuesday, 3/11/2008, 16:30-18:00, Room 02 3.2 System Synthesis (Session) Thursday, 3/12/2008, 16:00-17:30, Room 04 11.1 New Directions and Challenges (Dependable Embedded Systems Special Day, Panel Session) ... Read more | AbstractAn "embedded system" integrates both software and hardware to implement its functionality. However, the EDA industry has historically perceived "ESL" to mean system hardware design. The burgeoning software content of modern system on chip (SoC) solutions - together with the multiple processors required to execute that software - has changed that perception. The virtual system prototype (VSP), which the EDA industry considered to be the hardware designer’s view of the SoC, is now called a virtual platform and is used by software developers. ... Read more | ||
Person Index (Highlights)Wolfgang Ecker, Infineon Technologies AG, DE 1.1 Unifying or Overrated: A System Level Design Strategy Tuesday, March 11 11:30-13:00, Room 05 (Executive) W4 The New Wave of the High-Level Synthesis Friday, March 14 8:30-16:45, Room 03 (Speaker) Rolf Ernst, TU Braunschweig, DE 1.1 Unifying or Overrated: A System Level Design Strategy Tuesday, March 11 11:30-13:00, Room 05 (Executive) Ken Karnofsky, MathWorks, UK 1.1 Unifying or Overrated: A System Level Design Strategy Tuesday, March 11 11:30-13:00, Room 05 (Executive) Grant Martin, Tensilica, US A Automatically Realising Embedded System from High-Level Functional Models Monday, March 10 9:30-18:00, Room 11a (Speaker) Alberto L. Sangiovanni-Vincentelli, UC Berkeley, US XT4 Functional Design is all that matters? Wednesday, March 12 10:30-10:30, Exhibition Theater (Panelist) Gary Smith, Gary Smith EDA, US XT5 Concurrency in a Multi Processor World Wednesday, March 12 13:30-14:30, Exhibition Theater (Moderator) Dominique Vernay, CTO, THALES, Paris, FR Plenary: Perspective on Embedded Systems: Challenges and Research Priorities (Keynote) Tuesday, March 11 09:50-10:30, Room 13 (Keynote Speaker) ... Read more | Guest Comment
Gary Smith, Gary Smith EDA Embedded Systems - a Market in CrisisOver ten years ago we started out on the great SoC adventure. Initially, an SoC was defined as an ASIC with at least one element that was programmed by software. Soon we saw SoCs that had added a DSP or some other sort of co-processor to the mix. By 2001, we were embedding complete platforms into our SoCs and now we are placing multiple platforms into our SoCs. That means we are using multiple platforms that use multiple processors, producing an extremely complicated embedded system design. Unfortunately, it took us a long time to come to terms with the embedded software aspect of our designs. In 2001, we started seeing SoCs being designed that could not be programmed. Unfortunately, we had to produce finished silicon before we found that out. Our embedded tools were developed for computer board design, where the architecture was standard Von Neumann using one processor. ... Read more | ||
News & Background
CoWare and STARC Integrate SystemC TLM Methodology Design & Reuse, January 24, 2008 ... Read more | DATE in the News
Automotive, applications dominate DATE 08 EETimes, January 30, 2008 ... Read more | DATE LinksDATE in the web:
... Read more |
An "embedded system" integrates both software and hardware to implement its functionality. However, the EDA industry has historically perceived "ESL" to mean system hardware design. The burgeoning software content of modern system on chip (SoC) solutions - together with the multiple processors required to execute that software - has changed that perception.
The virtual system prototype (VSP), which the EDA industry considered to be the hardware designer’s view of the SoC, is now called a virtual platform and is used by software developers. The system hardware designer still uses ESL for the high-level modeling and analysis of hardware function, architecture, and power consumption, and for high-level synthesis. But now, the software developer uses faster, even higher level system hardware models for early software development. And the software has become a vital component in the hardware design verification suite.
Each of these design views has a different level of abstraction, but both use the established platform-based SoC design approach. The SoC platform’s ready-made, scalable architecture enables rapid derivative design, eliminating "design from scratch". As usual, the platform deploys re-usable hardware building blocks such as processors, memories, peripherals, and interconnect - both 3rd-party and internally-developed intellectual property (IP). But now, the software IP is also an essential part of the platform.
With so much functionality implemented in software, the design can meet its performance, power, and/or fail-safe requirements only by using multiple processors. The processors can be homogeneous, which has the potential to utilize automatic software scheduling, or they can be heterogeneous, which requires extensive manual scheduling effort. Either way, dealing with parallel software processing is a complex task - a task that mandates the use of ESL modeling and analysis.
Not surprisingly, this year’s DATE received 50% more ESL design and embedded software paper submissions than last year. Moreover, the "Dependable Embedded Systems Special Day" on Thursday reflects the importance of HW/SW co-development. Numerous papers from adjacent application and development areas such as automotive applications and system verification establish a comprehensive picture of the current research and its future application.
ESL is finally living up to its original promise - true HW/SW co-development. And by addressing the electronic system design challenge in its entirety, DATE-08 is living up to its reputation as the world’s premier conference for system level design.
Don’t miss it!
Gary Smith, Gary Smith EDA
Gary Smith is the founder and Chief Analyst for Gary Smith EDA. Previously, he was the Managing Vice President and Chief Analyst of the Electronic Design Automation Service, Design & Engineering Cluster at Gartner Dataquest.
Prior to joining Gartner, Mr. Smith was a consultant in design methodology and worked in the ASIC end of the semiconductor business. While at LSI Logic, Mr. Smith became an evangelist for the RT-level design methodology. Starting in the semiconductor industry, Mr. Smith was involved in some of the first attempts at customer-designed ICs.
Over ten years ago we started out on the great SoC adventure. Initially, an SoC was defined as an ASIC with at least one element that was programmed by software. Soon we saw SoCs that had added a DSP or some other sort of co-processor to the mix. By 2001, we were embedding complete platforms into our SoCs and now we are placing multiple platforms into our SoCs. That means we are using multiple platforms that use multiple processors, producing an extremely complicated embedded system design.
Unfortunately, it took us a long time to come to terms with the embedded software aspect of our designs. In 2001, we started seeing SoCs being designed that could not be programmed. Unfortunately, we had to produce finished silicon before we found that out. Our embedded tools were developed for computer board design, where the architecture was standard Von Neumann using one processor. These tools just didn’t work on our multi-core non-Von Neumann SoCs. The embedded vendors are still playing catch-up today.
What is complicating the problem is that they are chasing a moving target. Since the adoption of C as our standard programming language, we have addressed parallelism using threads. The limitation for using threads is spelled out in Amdahl’s Law. Basically we were talking about using hundreds of processors when the only applications that could actually use them were Embarrassingly Parallel Programs. Any general purpose computing application runs out of steam at four processors. It became obvious that threading wasn’t the answer, but we realized that only three years ago.
By the end of 2005, the microprocessor vendors had settled on the API, or library, approach to parallelism. The assumption was that C would remain the dominant programming language, so we needed a method of modifying the C code into a parallel program. This meant an intention layer above the C code, the development of a concurrent software compiler that targeted a scheduler macro embedded into the silicon. A group of start-ups, both from EDA and the Silicon IP world took on the challenge.
And then there was DATE 2007. What we saw at DATE were researchers starting to look at the algorithms themselves. The research concentration was changing to address the limitations of Amdahl’s Law itself. This continued at the usual conferences (EDP 2007, DAC 2007), but ended up surprisingly enough at ICCAD 2007, normally an IC layout conference. It seems that their problem was that the back-end IC tools had to move to a parallel architecture. In essence, the present tools were breaking at a hundred million gates, and the use of a multi-processor environment was the only way they could get adequate performance. The final discussion was on a panel following a talk by Gene Amdahl. In answering a question, Gene said that there was no way around Amdahl’s Law; all you could do was rewrite the algorithm. Once you accept that the development of parallel algorithms is the answer, it becomes obvious that we need a concurrent language to optimize the programming. The question is who, besides the embedded engineer, will use that language, but that is a discussion for another time.
So, the bottom line is that we need a whole new set of embedded tools to address the embedded systems challenges. Unfortunately we need them soon. In 2007, the cost of developing the software for an SoC surpassed the cost of designing that SoC, and it’s getting worse. The ITRS has determined that if we do not have a concurrent programming environment in place by 2013, our ability to remain on the Moore’s Law curve is in jeopardy. And just to make the job more exciting, we don’t even know what language we’ll be using. Maybe we’ll find out at DATE 2008.
9:30-18:00, Room 11a
To keep pace with the rising computational demands of embedded applications, an effective approach is to raise the level of abstraction at which the design of essential functionality is performed. Raising the level of abstraction allows designers to remove the complexity of low-level and implementation details, thereby gaining design productivity. However, raising the level of abstraction also widens the gap between design and implementation. To overcome the gap between design and implementation, this tutorial demonstrates technologies for: (i) the automatic transformation of the design into increasingly detailed representations, (ii) checking correctness of the additional detail, and (iii) hardware/software codesign. Model-Based Design is introduced and experts from industry and academia demonstrate the use of technologies such as automatic C and HDL code generation, automatic test bench generation, automatic sequential design refinement, and multi-domain system design, including mixed-signal simulation. The attendees will learn how to develop high-level domain specific models of embedded systems and how to exploit automatic transformation technology to systematically realize the embedded application. ... Read more
9:30-18:00, Room 03
Advanced embedded devices such as multi-standard mobile terminals demand ever-increasing performance and energy efficiency. Simultaneously, a high degree of flexibility and programmability is required due to increasing software complexity and fast changing protocol and codec standards. This has led to the concept of MPSoC (Multi-Processor System-on-Chip) platforms. In many cases, MPSoCs are simply assembled in "best effort" manner from existing legacy IP components, and programming the platform presents a major bottleneck. As Moore´s Law permits us to enter the "manycore" MPSoC area, what is needed is a systematic approach that builds on well-proven technologies, but also innovates with novel classes of electronic system-level (ESL) design automation tools. This tutorial discusses several key questions with significant impact on the future of MPSoC: What are the MPSoC killer applications? Is homogeneous or heterogeneous architecture the right choice? What are the key tools, methodologies and programming models for successfully designing and programming MPSoC platforms? In the end, will there be only a few survivor platforms that everyone has to accept? Based on their extensive research and industry experience, the presenters will provide their answers from a practical, application-oriented perspective. ... Read more
9:30-13:00, Room 04b
Every development of a complex, heterogeneous embedded system today is model based. Sound and well understood models are a necessary basis for all design, analysis and verification activities. However, most modelling practices used by industry often lack of methodological foundations being based on 'ad-hoc' solutions. But as it will be shown in this tutorial, theoretical concepts of Models of Computation and Communication (MoCC) can still be of practical use in industrial design flows by use of proper libraries, methodologies and modeling rules. ... Read more
14:30-18:00, Room 04b
Formal analysis and optimization of networked real-time systems has reached industrial maturity and is now regularly used, e.g. in automotive system design. More recently, such formal methods have been extended to MpSoCs, as a complement to simulation in order to improve predictability and reach performance guarantees. ... Read more
9:50-10:30, Room 13
Dominique Vernay, CTO, THALES, Paris, FR (Keynote Speaker)The societal demands in Europe for Health, Security & Safety, Energy and the market demands in nomadic, transport, communications, entertainment products, ask for innovations and technical leadership. Enabling embedded Systems require new challenging solutions like multi-physics devices, millions of interconnected nodes, very low power for autonomy, trusted and safe operations, reliability. The talk will introduce THALES vision and research priorities for embedded systems and will illustrate them through presentations of solutions and on-going research projects and initiatives. Thales effort related to mission-critical systems is focused on advanced high-performance embedded computing platforms, on middleware technologies, on software systems design and verification tools for safety and security and on the emergence of open standards in these domains. THALES is also actively contributing to the development of innovation eco-systems: the Joint Undertaking ARTEMIS in Europe; the Pôle de Compétitivité SYSTEM@TIC PARIS REGION in France. ... Read more
10:45-11:45, Exhibition Theater
Over the last few years, the ever-growing design complexity and design challenges associated with criticality of power, growing design-verification gap, inefficiencies of the logical-physical iterations, lack of clear implementation test and validation checkpoints, and the unpredictable nature of the ad-hoc iterative design process, have created the need for a fundamental shift in the way design is done. The result of the mounting challenges in design, coupled with the piecewise evolution of design methods has led to a crisis in the schedule predictability of chip programs.Those design teams that do make the tough decisions for change in their design process will be rewarded with capabilities to make more competitive designs faster and cheaper, with a critical advantage in design process predictability and shipping products to market on time or ahead of timeThis panel will look at why there is a schedule predictability crisis, and if single vendor integrated flows, flow management solutions, engineering group cross collaboration and/or adoptionof industry standards are a means to solve the crisis. ... Exhibition Program
11:30-13:00, Room 05
Significant momentum is building around ESL (Electronic System Level) design, but is the concept living up to much hyped expectations? Is there even a common definition for ESL? ESL models implemented in extensions to C/C++ have been applied in several design activities, including system analysis, SW/HW partitioning, and high-speed simulation. Yet, the promise of ESL for addressing the RTL verification gap is under-served where functional verification of ESL models is a pre-requisite for improving RTL verification. Simply stated, how are designs being implemented at the system level, and what level of automation is used? Are there trends in design architecture to advance automation? If standard practices are used to start at ESL and refine into a manufacturable representation, what are the options, problems and opportunities that design and verification teams encounter? What are the missing pieces? Once new levels of automation become mainstays in the design and verification flow, what are ‘next’ generation abstraction trends that will more tightly unify the system and RTL level methodologies, and create a basis for what the future will bring? ... Read more
11:30-13:00, Room 02
TLM is becoming a widely used technique for system modeling and performance estimation. Its practical application for system design still requires of additional research. In the first paper, TLM is proposed for system-level performance estimation. The second paper present a technique for automatic generation of timed from untimed models. The third paper addresses the automatic generation of RTL IPs into TLM models. ... Read more
11:30-13:00, Room 04a
An application specific instruction set processor for SDR and a reconfigurable memory interface present core achievements for reconfigurable systems. Two presentations on embedded FPGA architectures and their optimization conclude the session. ... Read more
13:30-14:30, Exhibition Theater
High frequencies and submicron feature size make predicting and managing power consumption of next-generation SoCs one of the major issues of the wireless industry. Power is also critical in home applications SoCs as high dissipation levels require expensive packaging and cooling. Tradeoff between overall systemperformance and power requirements have to be analyzed as soon as possible in such designs.Furthermore, functions related to dynamic power as well as thermal considerations affecting leakage currents which greatly impact battery life and system reliability need to be taken intoconsideration at the earliest stage.Are ESL solutions now able to address such issues earlier in thedesign flow in order to better anticipate power consumption of the whole system?ESL vendors and wireless chip and device manufacturers will debate various industry innovations to predict power consumption in complex multi-core SoCs earlier in the design flow.Panelists will give their viewpoints on the best way to anticipate power consumption profiles in order to design the right architecture which meets today's ever-increasing power requirements. ... Exhibition Program
16:30-18:00, Room 02
This session focusses on several system level synthesis aspects. Temperature awareness is becoming of increasing importance due to reliabities issues. The first paper integrates thermal modelling with task scheduling and can be considered to be one of the first papers in this area. The increasing number of bus protocols and the need to provide converters between these protocols is the topic of the second paper, taking this area a significant step forward. The third paper proposes a technique for reducing the number of cache misses in dataflow-oriented applications. The fourth paper describes the synthesis of latency-insensitive designs from a rule-based language. ... Read more
8:30-10:00, Room 04
The session spans verification solutions relying on high-level models of a design. The first paper focuses on evaluating the coverage of a test suite by perturbating the corresponding design model, while the second strives to boost coverage by targeting hard-to-reach corner cases. The third and fourth papers focus on debugging techniques, the former through a new maxSAT algorithm and the latter by means of a new debug structure to use in post-silicon functional verification via on- chip logic analyzers. The interactive presentations are centered on automatic design of hardware models. ... Read more
8:30-10:00, Room 04b
Model-based methods are increasingly adopted in industry for the design of complex engineered systems. This session illustrates Model- Based Design and the following methodologies and technologies: timed automata and testing, compositional scheduling using event models, formal foundations for tool coupling for hybrid systems, and a workflow for heterogeneous system synthesis. ... Read more
10:30-10:30, Exhibition Theater
Consensus in the industry seems to be that design must move to higher levels of abstraction. When that happened in the mainstream computing world, lower level development became almost totally automated. Will that happen in the EDA world? Will lower levels of design, including architectural definitions, be completely automated leaving higher-level, functional design being the only part of the design process that matters? This panel will examine these issues and discuss how higher-level design must evolve if it is to be the pinnacle of the design process. ... Exhibition Program
13:30-14:30, Exhibition Theater
Energy consumption, time to market and cost issues present technical challenges to design teams trying to satisfy the increasing consumer demands for more performance and at lower cost. The move to multiprocessors is to prevent the increase in clock speed -e.g. to avoid the power hit that higher frequencies entail. This is causing an increased number of processors in all consumer devices, and inconveniently breaking existing sequential software. To make matters worse, marketing hype and unclear terminology of multiprocessing, multicore and MPSoC continues to create confusion among designers and software developers of what the issues really are and how they can be tackled. ... Exhibition Program
15:45-16:45, Exhibition Theater
"Virtual Platforms”have been the ESL buzzwords for the last two years. They come with the promise of enabling early HW/SW integration, architectural exploration, and full system validation. But are they actually being deployed? And are they achieving the benefits promised by their proponents? Even if they are, what does it take to get to successful deployment? Which factor is most important in determining success: tools, models, or, in the end, services? What role do open standards such as SystemC play versus proprietary modeling approaches? Do customers even care about standards? Why or why not?And finally: Will Virtual Platforms pose a challenge to hardwareemulation solutions? Or is it just the opposite: Virtual Platforms will get all the hype, while hardware emulators will get all the money? This panel will attempt to shed light on these questions by bringing together representatives from semiconductor and system houses, tool providers, IP providers, and hardware emulation providers for what should prove to be a controversial and lively debate. ... Exhibition Program
16:30-18:00, Room 04b
This session on saftey-driven embedded systems design addresses reliability, fault-tolerance, and composability that ensures temporal and functional correctness. The first paper proposes a joint schedulability and reliability analysis of safety-critical real-time embedded applications. The second paper addresses scheduling of k fault-tolerant hard real-time tasks in the presence of soft real- time tasks with utility functions. The third paper presents tool support for automated incremental component-based failure mode and effects analysis of software and hardware. The fourth and last paper in this session proposes a way of safely composing synchronous components in globally asynchronous designs based on checking that the composition is non-blocking. ... Read more
11:00-12:30, Room 02
Memory continues to dominate the cost, power and performance aspects of VLSI systems. This special session focuses on how future NOC based Systems will deal with the memory challenge. This question is answered from three different perspectives in three presentations: the opportunities of 3D integration technology, the requirements of consumer electronics applications on the memory and communication architecture, and the challenges for future design methodologies. ... Read more
11:00-12:30, Room 12
This session discusses transparent acceleration of heterogeneous embedded applications, automatic selection of application-specific processor extensions, and MPI-based communication for highly parallel signal processing systems. ... Read more
14:00-15:30, Room 05
his session discusses new dynamic mapping techniques onto NoC-based MPSoCs and flow control techniques for on-chip communication. The first paper presents a novel dynamic resource allocation algorithm. The second paper proposes a new buffer minimisation approach in NoC routers. The third papers proposes a flow control mechanism scheme for on-chip networks based on global information. ... Read more
14:00-15:30, Room 13a
This session contains a spectrum of papers including high-level architectural exploration, neural network applications, online placement, and communications infrastructure design for heterogeneous architectures. ... Read more
16:00-17:30, Room 04
We conclude the special day on dependable embedded systems with a session to discuss the future of dependable embedded systems: new challenges, new directions and approaches. ... Read more
8:30-16:45, Room 03
The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimised gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioral one. Languages like C/C++/SystemC offer high abstraction levels. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools are required. Several commercial and academic tools are available today: Bluespec from Bluespec, Catapult from Mentor Graphics, Cyber from NEC, Cynthesizer from Forte Design Systems, PICO from Synfora … GAUT from UBS University, SPARK from UCSD, UGH from TIMA/LIP6, xPilot from UCLA… The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows a better coping with the system design complexity, to verify earlier in the design process and to increase code reuse. Target Audience: This workshop on High-Level Synthesis will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in this domain. It will give an outline of HLS methods and tools available currently on the market and bring the details on their applicability, performance, and strengths. Finally, the event will create a discussion platform for experience exchange between providers of synthesis technology and industry users. ... Read more
8:45-16:30, Room 02
The never ending expectations of increased computing performance and flexibility to chip architectures are the drivers for the development of new hardware approaches. Novel technologies, based on reconfigurable hardware could be a solution to handle the computation intensive tasks, e.g. for image and signal-processing. The challenge here is to find an optimal trade-off between power consumption, performance and flexibility which leads to the question which technology will be used in future systems. CPUs, coarse/ fine-grained reconfigurable architectures or heterogeneous approaches need to be considered. Nanotechnology and Mixed-Signal architectures, and also the introduction of new communication architectures like Networks-on-Chip are the keywords for the design of Multiple Processor System on Chip (MPSoC). The question for the system designers is to choose the optimal granularity for the run-time reconfigurable hardware as well as for the processor IP cores. Introducing novel architectures always means to provide tools for industrial development. Tool-integration and supplier support, specification and verification are here the challenges to provide new technologies to the industry. The question is how new tools can be embedded into existing development methods and designflow? The purpose of this workshop is to evaluate strategies for future system design in reconfigurable hardwaresystem-architectures. Both aspects, hardware design and tool-integration into existing development tools will be discussed. Especially the novel trends in Mixed-Signal reconfigurable architectures are a main topic in this workshop. The main emphasis is on architectures, design-flow, tool-development, applications and system design. The workshop is targeted for hardware and system engineers as well as to researchers from academics and industry. ... Read more
Samar Abdi, UC Irvine, US
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Author)
Jacob A. Abraham, U Texas at Austin, US
11.1 New Directions and Challenges (Dependable Embedded Systems Special Day)
Thursday, March 13 16:00-17:30, Room 04 (Panelist)
M A Al Faruque, Karlsruhe U, DE
10.2 Application Mapping onto NoCs and Flow Control
Thursday, March 13 14:00-15:30, Room 05 (Speaker)
Gerd Ascheid, RWTH Aachen, DE
C System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures
Monday, March 10 9:30-18:00, Room 03 (Speaker)
Tom Ashby, IMEC, BE
C System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures
Monday, March 10 9:30-18:00, Room 03 (Speaker)
D Atienza, DACYA/Madrid Complutense U, ES
10.2 Application Mapping onto NoCs and Flow Control
Thursday, March 13 14:00-15:30, Room 05 (Moderator)
K Avnit, New South Wales U, AU
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
Twan Basten, Twente U, NL
10.2 Application Mapping onto NoCs and Flow Control
Thursday, March 13 14:00-15:30, Room 05 (Moderator)
Juergen Becker, Karlsruhe Institute of Technology, DE
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Moderator)
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker, Organizer)
XT1 The Schedule Predictability Crisis - Can it be solved?
Tuesday, March 11 10:45-11:45, Exhibition Theater (Moderator)
Marco Bekooij, NXP Semiconductors, NL
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
F2 Formal Methods in System and MPSoC Performance Analysis and Optimisation
Monday, March 10 14:30-18:00, Room 04b (Speaker)
Valeria Bertacco, U Michigan, US
4.2 High-Level Models for Validation
Wednesday, March 12 8:30-10:00, Room 04 (Moderator)
Koen Bertels, TU Delft, NL
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Moderator)
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker, Organizer)
L Besnard, CNRS, FR
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
J Beutel, ETH Zurich, CH
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Moderator)
Thomas F. Blaesi, ChipVision Design Systems AG, DE
XT2 ESL Solutions for power prediction in wireless
Tuesday, March 11 13:30-14:30, Exhibition Theater (Panelist)
S Bocchio, STMicroelectronics, IT
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Moderator)
T Bollaert, Mentor Graphics, FR
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
N Bombieri, Verona U, IT
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Speaker)
4.2 High-Level Models for Validation
Wednesday, March 12 8:30-10:00, Room 04 (Speaker)
Philippe Bonnot, Thales Research and Technology, FR
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Speaker)
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
E Brinksma, Embedded Systems Institute, FR
4.6 Model-Based Design for Embedded Systems
Wednesday, March 12 8:30-10:00, Room 04b (Moderator)
L Brisolara, UFRGS, BR
4.6 Model-Based Design for Embedded Systems
Wednesday, March 12 8:30-10:00, Room 04b (Speaker)
Luc Burgun, EVE USA, Inc., FR
XT7 Virtual Platforms: ESL Hype or Killer App?
Wednesday, March 12 15:45-16:45, Exhibition Theater (Panelist)
Misha Buric, Altera, US
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Executive)
F Campi, STMicroelectronics, IT
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Speaker)
Steve Carlson, Cadence Design Systems, US
XT1 The Schedule Predictability Crisis - Can it be solved?
Tuesday, March 11 10:45-11:45, Exhibition Theater (Panelist)
Christos Cassandras, Boston U, US
A Automatically Realising Embedded Systems from High-Level Functional Models
Monday, March 10 9:30-18:00, Room 11a (Speaker)
Samarjit Chakraborty, National U Singapore, SG
F2 Formal Methods in System and MPSoC Performance Analysis and Optimisation
Monday, March 10 14:30-18:00, Room 04b (Speaker)
T Chantem, Notre Dame U, US
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
A Chattopadhyay, RWTH Aachen U, DE
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Speaker)
C-L Chou, Carnegie Mellon U, US
10.2 Application Mapping onto NoCs and Flow Control
Thursday, March 13 14:00-15:30, Room 05 (Speaker)
J Cong, UCLA / AutoESL, US
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
B Cope, Imperial College London, UK
1.4 Application of Reconfigurable and Adaptive Systems
Tuesday, March 11 11:30-13:00, Room 04a (Speaker)
J Cornet, Verimag / STMicroelectronics, FR
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Speaker)
P Coussy, U of South Britanny UBS, Laster Lab., FR
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker, Chair, Speaker)
Leslie Cumming, Skye Comms, US
XT5 Concurrency in a Multi Processor World
Wednesday, March 12 13:30-14:30, Exhibition Theater (Organizer)
V D'Silva, ETH Zurich, CH
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
A David, Aalborg U, DK
4.6 Model-Based Design for Embedded Systems
Wednesday, March 12 8:30-10:00, Room 04b (Speaker)
Simon Davidmann, Imperas, US
XT5 Concurrency in a Multi Processor World
Wednesday, March 12 13:30-14:30, Exhibition Theater (Panelist)
N Deganello, Verona U, IT
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Author)
A Deledda, Bologna U, IT
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Speaker)
Robert P. Dick, Northwestern University, US
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
Mark Dickinson, Altera Europe, UK
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Antun Domic, Synopsys, US
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Organizer)
Wolfgang Ecker, Infineon Technologies AG, DE
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Executive)
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
J Elmqvist, Linkoping U, SE
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
Carl Engblom, Ericsson, SE
XT5 Concurrency in a Multi Processor World
Wednesday, March 12 13:30-14:30, Exhibition Theater (Panelist)
Rolf Ernst, TU Braunschweig, DE
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Executive)
F2 Formal Methods in System and MPSoC Performance Analysis and Optimisation
Monday, March 10 14:30-18:00, Room 04b (Speaker, Organizer)
Robert Esser, Xilinx Inc., IE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
A Farmahini-Farahani, Tehran U, IR
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Speaker)
Christof Fetzer, TU Dresden, DE
11.1 New Directions and Challenges (Dependable Embedded Systems Special Day)
Thursday, March 13 16:00-17:30, Room 04 (Organizer)
Dietmar Fruehauf, Endress & Hauser GmbH, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
F Fummi, Verona U, IT
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Author)
Daniel D. Gajski, UC Irvine, US
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Author)
Christian Gamrat, CEA Paris, FR
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Robert Gardner, EDA Consortium, US
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Organizer)
G Gaydadjiev, TU Delft, NL
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Speaker)
L Gheorghe, Ecole Polytechnique de Montreal, CA
4.6 Model-Based Design for Embedded Systems
Wednesday, March 12 8:30-10:00, Room 04b (Speaker)
A Ghosal, UC Berkeley, US
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
Christoph Grimm, TU Vienna, AT
F1 Heterogeneous System-level Specification Using SystemC
Monday, March 10 9:30-13:00, Room 04b (Speaker)
Gargan Gupta, ARC International, UK
XT1 The Schedule Predictability Crisis - Can it be solved?
Tuesday, March 11 10:45-11:45, Exhibition Theater (Panelist)
R Gupta, University of California, San Diego, US
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
Ian G. Harris, UC Irvine, US
4.2 High-Level Models for Validation
Wednesday, March 12 8:30-10:00, Room 04 (Moderator)
Christoph Heer, Infineon, DE
1.4 Application of Reconfigurable and Adaptive Systems
Tuesday, March 11 11:30-13:00, Room 04a (Moderator)
J Heighton, Xilinx, IR
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
A Hemani, Royal Institute of Technology, SE
9.2 The Memory Challenge in NoC Based Systems
Thursday, March 13 11:00-12:30, Room 02 (Moderator, Organizer)
T A Henzinger, EPFL, CH
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
Paul Heysters, Recore Systems, NL
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
G Hoover, UC Santa Barabara, US
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
Robert Hum, Mentor Graphics, US
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Moderator)
Andrea Huse, Cadence Design Systems GmbH, DE
XT1 The Schedule Predictability Crisis - Can it be solved?
Tuesday, March 11 10:45-11:45, Exhibition Theater (Organizer)
Y Hwang, UC Irvine, US
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Speaker)
Michael Huebner, Karlsruhe U, DE
1.4 Application of Reconfigurable and Adaptive Systems
Tuesday, March 11 11:30-13:00, Room 04a (Moderator)
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Moderator)
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Organizer)
D Iercan, Politehnica U of Timisoara, RO
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
Viacheslav Izosimov, Linkoping U, SE
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
Axel Jantsch, Royal Institute of Technology, SE
9.2 The Memory Challenge in NoC Based Systems
Thursday, March 13 11:00-12:30, Room 02 (Moderator, Organizer)
F1 Heterogeneous System-level Specification Using SystemC
Monday, March 10 9:30-13:00, Room 04b (Speaker)
Ahmed Amine Jerraya, CEA, FR
XT4 Functional Design is all that matters?
Wednesday, March 12 10:30-10:30, Exhibition Theater (Panelist)
Ahmed Jerraya, CEA-LETI, FR
A Automatically Realising Embedded Systems from High-Level Functional Models
Monday, March 10 9:30-18:00, Room 11a (Speaker)
Marek Jersak, Symtavision, DE
F2 Formal Methods in System and MPSoC Performance Analysis and Optimisation
Monday, March 10 14:30-18:00, Room 04b (Speaker)
Ghislain Kaiser, DoceaPower, FR
XT2 ESL Solutions for power prediction in wireless
Tuesday, March 11 13:30-14:30, Exhibition Theater (Panelist)
Ken Karnofsky, MathWorks, UK
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Executive)
Ryan Kastner, UCSB, US
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
V Katail, Synfora, US
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
Dr. Austin Kim, Samsung Electronics, KP
XT4 Functional Design is all that matters?
Wednesday, March 12 10:30-10:30, Exhibition Theater (Panelist)
C Kirsch, Salzburg U, AT
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
Tim Kogel, CoWare, NN
F1 Heterogeneous System-level Specification Using SystemC
Monday, March 10 9:30-13:00, Room 04b (Speaker)
Klaus Kronlöf, Nokia Research Center, FI
XT2 ESL Solutions for power prediction in wireless
Tuesday, March 11 13:30-14:30, Exhibition Theater (Panelist)
Wido Kruijtzer, NXP Semiconductors, NL
A Automatically Realising Embedded Systems from High-Level Functional Models
Monday, March 10 9:30-18:00, Room 11a (Speaker)
Joachim Kruecken, Freescale Semiconductor, DE
XT1 The Schedule Predictability Crisis - Can it be solved?
Tuesday, March 11 10:45-11:45, Exhibition Theater (Panelist)
Krzysztof Kuchcinski, Lund U, SE
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Speaker)
M Kuehnle, Karlsruhe U, DE
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Speaker)
Joachim Kunkel, Synopsys, US
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Executive)
XT7 Virtual Platforms: ESL Hype or Killer App?
Wednesday, March 12 15:45-16:45, Exhibition Theater (Panelist)
W-C Kwon, Samsung Electronics, KR
10.2 Application Mapping onto NoCs and Flow Control
Thursday, March 13 14:00-15:30, Room 05 (Speaker)
Rudy Lauwereins, IMEC, BE
XT5 Concurrency in a Multi Processor World
Wednesday, March 12 13:30-14:30, Exhibition Theater (Panelist)
Rainer Leupers, RWTH Aachen, DE
C System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures
Monday, March 10 9:30-18:00, Room 03 (Speaker, Organizer)
W. Luk, Imperial College London, UK
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Moderator)
Nicolas Mading, IBM Deutschland Entwicklung, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Laurent Maillet-Contoz, STMicroelectronics, FR
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Speaker)
F Maraninchi, Verimag, FR
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Speaker)
T Marconi, TU Delft, NL
10.7 Reconfigurable Architectures and Run-Time Optimisations
Thursday, March 13 14:00-15:30, Room 13a (Speaker)
J Marques-Silva, Southampton U, UK
4.2 High-Level Models for Validation
Wednesday, March 12 8:30-10:00, Room 04 (Speaker)
Grant Martin, Tensilica, US
A Automatically Realising Embedded Systems from High-Level Functional Models
Monday, March 10 9:30-18:00, Room 11a (Speaker)
XT5 Concurrency in a Multi Processor World
Wednesday, March 12 13:30-14:30, Exhibition Theater (Panelist)
A Mendelson, Intel, IL
11.1 New Directions and Challenges (Dependable Embedded Systems Special Day)
Thursday, March 13 16:00-17:30, Room 04 (Panelist, Speaker)
M Meredith, Forte Design Systems, US
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
Subhasish Mitra, Stanford U, US
11.1 New Directions and Challenges (Dependable Embedded Systems Special Day)
Thursday, March 13 16:00-17:30, Room 04 (Panelist)
A Moonen, TU Eindhoven, NL
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
Adam Morawiec, ESCI, FR
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Co-Chair)
Pieter J. Mosterman, The MathWorks, US
4.6 Model-Based Design for Embedded Systems
Wednesday, March 12 8:30-10:00, Room 04b (Moderator)
A Automatically Realising Embedded Systems from High-Level Functional Models
Monday, March 10 9:30-18:00, Room 11a (Organizer)
Wolfgang Mueller, Paderborn U, DE
1.2 Transaction-Level Modelling (TLM)
Tuesday, March 11 11:30-13:00, Room 02 (Moderator)
Alan Naumann, CoWare, US
XT7 Virtual Platforms: ESL Hype or Killer App?
Wednesday, March 12 15:45-16:45, Exhibition Theater (Panelist)
B Neumann, IFAK e.V., DE
1.4 Application of Reconfigurable and Adaptive Systems
Tuesday, March 11 11:30-13:00, Room 04a (Speaker)
Rishiyur S. Nikhil, Bluespec, Inc., US
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
Peter Nord, Ericsson, SE
1.1 Unifying or Overrated: A System Level Design Strategy
Tuesday, March 11 11:30-13:00, Room 05 (Executive)
Don Orofino, The MathWorks, US
A Automatically Realising Embedded Systems from High-Level Functional Models
Monday, March 10 9:30-18:00, Room 11a (Speaker)
Maurizio Paganini, STMicroelectronics, IT
XT5 Concurrency in a Multi Processor World
Wednesday, March 12 13:30-14:30, Exhibition Theater (Panelist)
K Paulsson, U Karlsruhe, DE
1.4 Application of Reconfigurable and Adaptive Systems
Tuesday, March 11 11:30-13:00, Room 04a (Speaker)
Vincent Perrier, CoFluent Design, FR
XT2 ESL Solutions for power prediction in wireless
Tuesday, March 11 13:30-14:30, Exhibition Theater (Organizer, Panelist)
C Pinello, Cadence Berkely Lab, US
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
S Poledna, TTTech, AT
11.1 New Directions and Challenges (Dependable Embedded Systems Special Day)
Thursday, March 13 16:00-17:30, Room 04 (Panelist)
P Pop, DTU, DK
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Moderator)
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
F Pétrot, TIMA Laboratory, FR
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
S. Ramesh, GM India Science Lab, IN
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
Francois Remond, STMicroelectronics, FR
XT1 The Schedule Predictability Crisis - Can it be solved?
Tuesday, March 11 10:45-11:45, Exhibition Theater (Panelist)
Wolfgang Rosenstiel, edacentrum e.V., DE
XT7 Virtual Platforms: ESL Hype or Killer App?
Wednesday, March 12 15:45-16:45, Exhibition Theater (Moderator)
J Rox, TU Braunschweig, DE
4.6 Model-Based Design for Embedded Systems
Wednesday, March 12 8:30-10:00, Room 04b (Moderator)
M Rutzig, UFRGS, BR
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Speaker)
S Saha, U of Maryland, US
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Speaker)
Alberto L. Sangiovanni-Vincentelli, UC Berkeley, US
XT4 Functional Design is all that matters?
Wednesday, March 12 10:30-10:30, Exhibition Theater (Panelist)
Hans Sarnowski, BMW, NN
F2 Formal Methods in System and MPSoC Performance Analysis and Optimisation
Monday, March 10 14:30-18:00, Room 04b (Speaker)
Richard Scales, Texas Instruments, FR
XT2 ESL Solutions for power prediction in wireless
Tuesday, March 11 13:30-14:30, Exhibition Theater (Panelist)
J Schlessman, Princeton U, US
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Speaker)
A C Schneider Beck, UFRGS, BR and TU Delft, NL
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Speaker)
Guido Schreiner, MathWorks, DE
XT4 Functional Design is all that matters?
Wednesday, March 12 10:30-10:30, Exhibition Theater (Organizer)
Dr. Endric Schubert, ESIC GmbH, DE
XT4 Functional Design is all that matters?
Wednesday, March 12 10:30-10:30, Exhibition Theater (Moderator)
Eberhard Schueler, PACT, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Gary Smith, Gary Smith EDA, US
XT5 Concurrency in a Multi Processor World
Wednesday, March 12 13:30-14:30, Exhibition Theater (Moderator)
Mark Snook, ARM, UK
XT7 Virtual Platforms: ESL Hype or Killer App?
Wednesday, March 12 15:45-16:45, Exhibition Theater (Panelist)
Dr. Johannes Stahl, CoWare, US
XT4 Functional Design is all that matters?
Wednesday, March 12 10:30-10:30, Exhibition Theater (Panelist)
Neeraj Suri, TU Darmstadt, DE
11.1 New Directions and Challenges (Dependable Embedded Systems Special Day)
Thursday, March 13 16:00-17:30, Room 04 (Moderator, Organizer)
Janos Sztipanovits, Vanderbilt U, US
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Moderator)
A Automatically Realising Embedded Systems from High-Level Functional Models
Monday, March 10 9:30-18:00, Room 11a (Speaker)
Andres Takach, Mentor Graphics Corporation, US
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
J-P Talpin, INRIA, FR
7.6 Safety-Driven Embedded Systems Design
Wednesday, March 12 16:30-18:00, Room 04b (Speaker)
S Tang, The Chinese U of Hong Konk, CN
4.2 High-Level Models for Validation
Wednesday, March 12 8:30-10:00, Room 04 (Speaker)
Yankin Tanurhan, Actel Corp., US
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Juergen Teich, Erlangen-Nuernberg U, DE
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Moderator)
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Frans Theeuwen, NXP Semiconductors, NL
XT2 ESL Solutions for power prediction in wireless
Tuesday, March 11 13:30-14:30, Exhibition Theater (Panelist)
Alexander Thomas, Karlsruhe U, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Jim Tung, MathWorks, US
XT4 Functional Design is all that matters?
Wednesday, March 12 10:30-10:30, Exhibition Theater (Panelist)
Sharon Turnoy, Synopsys, Inc., US
XT7 Virtual Platforms: ESL Hype or Killer App?
Wednesday, March 12 15:45-16:45, Exhibition Theater (Organizer)
Pascal Urard, STMicroelectronics, FR
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
XT4 Functional Design is all that matters?
Wednesday, March 12 10:30-10:30, Exhibition Theater (Panelist)
J Van Meerbergen, Philips Reserach / TU Eindhoven, NL
3.2 System Synthesis
Tuesday, March 11 16:30-18:00, Room 02 (Speaker)
A Vandecappelle, IMEC, BE
C System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures
Monday, March 10 9:30-18:00, Room 03 (Speaker)
Wilfried Verachtert, IMEC, BE
C System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures
Monday, March 10 9:30-18:00, Room 03 (Speaker)
Dominique Vernay, CTO, THALES, Paris, FR
Plenary: Perspective on Embedded Systems: Challenges and Research Priorities (Keynote)
Tuesday, March 11 9:50-10:30, Room 13 (Keynotespeaker)
Eugenio Villar, U Cantabri, ES
F1 Heterogeneous System-level Specification Using SystemC
Monday, March 10 9:30-13:00, Room 04b (Speaker, Organizer)
T Vogt, TU Kaiserslautern, DE
1.4 Application of Reconfigurable and Adaptive Systems
Tuesday, March 11 11:30-13:00, Room 04a (Speaker)
K Wakabayashi, NEC, JP
W4 The New Wave of the High-Level Synthesis
Friday, March 14 8:30-16:45, Room 03 (Speaker)
Norbert Wehn, TU Kaiserslautern, DE
1.4 Application of Reconfigurable and Adaptive Systems
Tuesday, March 11 11:30-13:00, Room 04a (Author)
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Peter Wintermayr, Elektronik.net, DE
XT2 ESL Solutions for power prediction in wireless
Tuesday, March 11 13:30-14:30, Exhibition Theater (Moderator)
C Wolinski, Rennes I U and IRISA, FR
9.7 Acceleration of Reconfigurable Applications
Thursday, March 13 11:00-12:30, Room 12 (Speaker)
W Wu, Virginia Tech, US
4.2 High-Level Models for Validation
Wednesday, March 12 8:30-10:00, Room 04 (Speaker)
Roberto Zafalon, STMicroelectronics, IT
XT2 ESL Solutions for power prediction in wireless
Tuesday, March 11 13:30-14:30, Exhibition Theater (Panelist)
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Catalytic's Celoxica buy brings Matlab to FPGAs
SCDsource Newsletter, January 9, 2008
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OSCI TLM-2 proposal - the debate begins
SCDsource Newsletter, January 9, 2008
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Virtual platforms - a reality check, part 2
SCDsource Newsletter, January 2, 2008
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Imperas preps multicore virtual platform tools
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Virtual platforms - a reality check, part 1
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Optimized Mentor-MathWorks FPGA design flow
Programmable Logic DesignLine, November 15, 2007
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Automotive, applications dominate DATE 08
EETimes, January 30, 2008
http://eetimes.eu/germany/206100317
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