Welcome to the 6th issue of the DATE08 Preview, which addresses analog and mixed-signal design. Here, we provide a snapshot of the DATE08 program that covers this important topic, complemented by a commentary from Thomas Hoetzel, CTO of ZMD, together with additional news and background information.
For more previews please visit the DATE website: http://www.date-conference.com
We would also like to invite you to help us to improve.
Please send your feedback to: datepreviews@edacentrum.de.
| Abstract | Programme Excerpt |
Guest Comment |
Person Index |
News & Background |
DATE in the News |
DATE Links |
Programme Excerpt (Highlights)Tuesday, March 11 14:30-16:00, Room 03 2.3 New Directions in Analog Circuit Modelling (Session) Tuesday, March 11 15:45-16:45, Exhibition Theatre X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session) Tuesday, March 11 16:30-18:00, Room 03 3.3 Analog Simulation, Synthesis and Verification (Session) Thursday, March 13 14:00-15:30, Room 12 10.6 Analogue: How to Survive in the Era of Nano CMOS (Hot Topic) ... Read more | AbstractThe "digital" mobile phone in your pocket cannot work without analog and mixed analog/digital (A/MS) technology. Nor can your "digital" camera. Nor can your apparently highly-digitized automobile. Nor can any "digital" system that must process signals from a universe that works on firmly analog principles (excluding quantum effects, of course!). The bulk of EDA tools are targeted at automating digital design. The EDA industry leaves A/MS chips to be designed largely manually. But even the digital designer cannot escape analog reality - continual scaling of chip process technologies has taken digital physical design into the realm of analog engineering.
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Person Index (Highlights)A Doboli, State U of New York at Stony Brook, US 6.3 Robust Mixed-Signal System Design Wednesday, March 12 14:30-16:00, Room 03 (Moderator) Luca Fanucci, Pisa U, IT 10.6 Analogue: How to Survive in the Era of Nano CMOS (Hot Topic) Thursday, March 13 14:00-15:30, Room 12 (Moderator, Organizer) Georges Gielen, KU Leuven, BE D2 From Transistor to PLL - Analogue Design and EDA Methods Monday, March 10 14:30-18:00, Room 11b (Speaker) X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session) Tuesday, March 11 15:45-16:45, Exhibition Theatre (Moderator) 10.6 Analogue: How to Survive in the Era of Nano CMOS (Hot Topic) Thursday, March 13 14:00-15:30, Room 12 (Organizer) Helmut Graeb, TU Munich, DE D2 From Transistor to PLL - Analogue Design and EDA Methods Monday, March 10 14:30-18:00, Room 11b (Speaker) X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session) Tuesday, March 11 15:45-16:45, Exhibition Theatre (Panelist) 3.3 Analog Simulation, Synthesis and Verification Tuesday, March 11 16:30-18:00, Room 03 (Moderator) Christoph Grimm, TU Vienna, AT 2.3 New Directions in Analog Circuit Modelling Tuesday, March 11 14:30-16:00, Room 03 (Moderator) Thomas Harms, Infineon, DE E2 DfM in the Analogue and Digital World Monday, March 10 14:30-18:00, Room 04a (Speaker) Jaijeet Roychowdhury, U Minn Twin Cities, US D2 From Transistor to PLL - Analogue Design and EDA Methods Monday, March 10 14:30-18:00, Room 11b (Speaker) ... Read more | Guest Comment
Thomas Hötzel, ZMD AG, CTO Fabless companies have more and more access to the latest design technologies. As a consequence, the competition is more and more in the area of circuit design. There are challenges and huge opportunities for companies that invest in those upcoming methodologies that will significantly improve efficiency. Hence, analog and mixed-signal (A/MS) design is one of the most exciting areas of productivity improvement in semiconductors, especially in this decade. Substantial growth can be observed in the analog and mixed-signal semiconductor markets. Automotive is one of the key performance and quality drivers of analog and mixed-signal design and well presented at this year’s DATE event. The power segment is enabled by mixed-signal energy saving technologies to ensure environmental protection. And complex sensor system solutions enable health monitoring and safe automotive solutions while serving as the electrical interface to the real world. Energy harvesting devices with lowest power signal conditioning and ultra high performance computing at nanometer structures lie at the other extreme. To cope with the analog complexity, these businesses need analog experts and ‘artists’ ... Read more | ||
News & Background
Analog experts call for new methodologies SCD Source, Tets Maniwa, 08 February 2008 ... Read more | DATE in the News
DATE'08 Features European Research Projects EDA Geek, February 15, 2008 ... Read more | DATE LinksDATE in the web:
... Read more |
The "digital" mobile phone in your pocket cannot work without analog and mixed analog/digital (A/MS) technology. Nor can your "digital" camera. Nor can your apparently highly-digitized automobile. Nor can any "digital" system that must process signals from a universe that works on firmly analog principles (excluding quantum effects, of course!).
The bulk of EDA tools are targeted at automating digital design. The EDA industry leaves A/MS chips to be designed largely manually. But even the digital designer cannot escape analog reality - continual scaling of chip process technologies has taken digital physical design into the realm of analog engineering. Consequently, both A/MS and digital design now require analog design expertise and analog design tools.
The fact is that A/MS design is every bit as critical to commercial success as digital design. So, the current A/MS design productivity gap presents the EDA industry with a significant revenue growth opportunity.
These are the reasons why A/MS again occupies a prominent position at the DATE. The technical sessions cover analog circuit modeling, analog simulation, synthesis and verification, as well as BIST and robust A/MS design. There are two Monday workshops and one Friday tutorial that deal with analog-related topics. This year’s conference also features two discussions on the future prospects for A/MS:
Both panels will be moderated the eminent European authority on analog design, Professor Georges Gielen, head of the Analog and Mixed-Signal Design Methodologies subgroup of the ESAT-MICAS, Katholieke Universiteit Leuven.
There is a lot of analog and mixed-signal material at DATE08. Learn about it, meet the people, discuss the topics and see the tools. In short: don’t miss it!

Thomas Hötzel, ZMD AG, CTO
Thomas Hoetzel joined ZMD in 2005 as Chief Technology Officer. In April 2006, he was appointed to the Managing Board. Thomas has many years experience in Semiconductors Innovation Management. His expert knowledge covers the complete business process from strategy planning to mass production. Thomas studied electrical engineering at Carolo Wilhelmina Technical University Brunswick, focusing on multimedia before joining Philips Semiconductors in 1989. At his last Position in Philips Semiconductors now NXP, Thomas was responsible for the car infotainment business segment. From 2000 to 2005 he served as Chief Operating Officer at sci-worx GmbH, during these days a subsidiary of Infineon Technologies AG.
Fabless companies have more and more access to the latest design technologies. As a consequence, the competition is more and more in the area of circuit design. There are challenges and huge opportunities for companies that invest in those upcoming methodologies that will significantly improve efficiency. Hence, analog and mixed-signal (A/MS) design is one of the most exciting areas of productivity improvement in semiconductors, especially in this decade.
Substantial growth can be observed in the analog and mixed-signal semiconductor markets. Automotive is one of the key performance and quality drivers of analog and mixed-signal design and well presented at this year’s DATE event. The power segment is enabled by mixed-signal energy saving technologies to ensure environmental protection. And complex sensor system solutions enable health monitoring and safe automotive solutions while serving as the electrical interface to the real world. Energy harvesting devices with lowest power signal conditioning and ultra high performance computing at nanometer structures lie at the other extreme. To cope with the analog complexity, these businesses need analog experts and ‘artists’ more than any other design segment. Today we are far away from a complete and closed A/MS EDA tool chain, and still suffer from the "problem too big and market too small" syndrome. As a consequence, the analog design community looks enviously at the productivity progress achieved in digital design during the last decade.
One of the key challenges in A/MS is "right first time" silicon, combined with the commercial requirement to use highly cost efficient processes that do not always provide the best analog performance from the designer’s perspective. And this is getting worse while dealing with, for example, large device mismatches and very low voltages, which reduce the signal to noise ratio.
Novel analog/mixed-signal verification methodologies are expected to become one of the key productivity improvement enablers. They will support the design teams to answer the key question concerning analog regression and verification coverage: "When do you know that you are done?"
To improve robustness, quality has to be built-into the design in the concept phase. Given the complexity of an analog circuit design, high level modelling is one of the keys to efficient design optimization and verification and, finally, to first pass success. Improved methodologies and tools are key in the areas of DfX and vital enablers of zero defect quality.
Not only design capabilities but also test concepts are main contributors to product differentiation and cost competitiveness. Clever analog built-in self-test (BIST) structures and analysis methodologies reduce test cost and enable effective trace back capabilities of production issues into the design environment to shorten returned material analysis (RMA).
Here at DATE 08 you can see that all this is going to happen, just get in touch with the experts to prepare for the development in analog/mixed-signal design.
Upcoming new technologies and new approaches in these fields are being presented. How do we survive in the era of nano-CMOS, with dwindling reliability and the faster scaling of digital? Progress in analog synthesis is presented as one of the key technologies that will enable productivity increases in the next decade. Another trend is the demand for the increased computing performance and flexibility of multiprocessor system on chip (MPSoC) architectures, where novel reconfigurable mixed-signal sensor/actuator architectures are required, in addition to the much-discussed software. Trends in biological interfaces for DANN detection that require novel circuit architectures will widen your scope.
The DATE08 program addresses all of these issues - and more. That’s why the DATE is Europe’s largest electronic design conference. Can you really afford to miss it?
I am going to DATE because it reveals a variety of new exciting approaches and possible solutions that certainly will have an impact on my decisions to extend our leadership position in analog/mixed-signal design. EDA is getting serious about analog/mixed-signal, which is highly appreciated. At DATE you will discover this change happen - this is what makes it a most exciting and important event for ZMD. And of course I appreciate DATE as a basis for fruitful discussions between chip companies, EDA companies and academia.
I am looking forward to see you with my colleagues from ZMD at Date08.
And believe me, the world is analog!
14:30-18:00, Room 11b
Although analog and mixed-signal design is greatly complicated by numerous design choices, the management of these design choices presents significant opportunities for optimizing designs for desired tradeoffs in performance and high production yield. This tutorial describes analog design and EDA methods beginning with MOS transistors and concluding with PLLs as complete mixed-signal systems. ... Read more
14:30-18:00, Room 04a
No matter whether the designer thinks analog or digital, he is faced with the DfM issue. Although confronted with different challenges, the key for satisfying yield in production lies in the design phase. Tools, techniques, and methods that once worked without fail cannot hold up any longer. More of the responsibility for yield must shift to the designer, so the fabless model, where foundry information flows freely, increases in importance. ... Read more
11:30-13:00, Room 11
In this session, several BIST solutions for MS devices are presented. First, the Goetzel algorithm is used for test data evaluation. Next, a multivariate kernel estimator is used to estimate non-normality of performance densities to set BIST limits. Then, a new diagnostic analysis for ADCs is proposed using DfT structures. Finally, an implementation of a network analyzer for evaluation purposes on a test board is presented. ... Read more
14:30-16:00, Room 03
The three papers in this session address new fundamental technologies for automation of analog circuit design. A number of potentially high- impact developments are outlined, including sizing rules in bipolar circuit design, numerically efficient carbon nanotube transistor models as well as a new approach to yield and performance optimisation for behavioural analog integrated circuits. ... Read more
15:45-16:45, Exhibition Theatre
As the challenging and time-consuming verification process in general belongs to the top tenmain EDA issues for years, and aware of analog challenges mostly surpass digital ones, no one will deny that verification of analog circuit design is one of the most challenging topics within EDA. Apart from that, we witnessed formal methods on their triumphal procession defeating verification challenges of digital circuits like verification coverage and efficiency. A few years ago, fist academic approaches in formal verificationmethods for analog arose and since then, gained growing interest* despite other approaches like analog verification libraries. Formal approaches promise to lead to automated visibilityof critical design errors like unintentional oscillation and feedback loops. Nevertheless the criticism on formal methods never stops, because there are doubts concerning their applicability. Are designers willing to adopt strict formalism to their work? Are formal approaches able to stand the challenges of reality? Hence, the panel will discuss, if formal methods are outrider of the key to verification in analog or if it is just phantasm?
... Exhibition Program
*Since June 2006 a consortia of system and semiconductor companies, EDA companies and universities work on that topic within a public funded R&D project entitled Verification of Analog Circuits (VeronA, label: 01 M 3079).
German R&D-Project VeronA covers the verification of analog circuits: VeronA Project Website
16:30-18:00, Room 03
Papers in this session present new results in periodic steady-state and harmonic balance analyses for automated design of non-linear analog circuits, as well as a proposal for an analog specification language to support a new verification methodology of complex analog designs. ... Read more
14:30-16:00, Room 03
The challenges in modern deep submicron CMOS design include stringent requirements such as very low supply voltages, process variations and large device mismatches. This session presents four papers which discuss novel mixed-signal circuit and system design techniques to cope with these challenges: low-voltage design styles, temperature compensation, offset cancellation, and finally the upcoming topic of energy harvesting circuits. ... Read more
16:30-18:00, Room 05
The car of the future will be based on very advanced software and hardware technologies for improved safety and additional features such as autonomous driving, vehicle to vehicle communication, extensive communication and entertainment subsystems. What are the limiting factors for introducing new technology in cars? What are the standards, methods and tools that will be needed to bring these cars to market quickly and with guaranteed properties? The experts in the panel will address these questions and discuss their preferred solutions. ... Read more
14:00-15:30, Room 12
CMOS technology is entering the nanometer era with 65nm becoming the mainstream digital design node. For the analogue circuits this however poses serious challenges that need to be addressed by clever and innovative design techniques. This hot topic session addresses three of these problem areas and presents possible solutions. The reduction in supply voltage is a challenge for keeping up with the dynamic range requirements of the analogue circuits. The exploding variability and dwindling reliability of nanometer CMOS also requires special design techniques. Finally, emerging applications like bio interfaces (e.g. DNA detection) require novel circuit architectures, to balance all design constraints. Will analogue survive on the same chip as scaling digital? ... Read more
8:45-16:30, Room 02
The never ending expectations of increased computing performance and flexibility to chip architectures are the drivers for the development of new hardware approaches. Novel technologies, based on reconfigurable hardware could be a solution to handle the computation intensive tasks, e.g. for image and signal-processing. The challenge here is to find an optimal trade-off between power consumption, performance and flexibility which leads to the question which technology will be used in future systems. CPUs, coarse/ fine-grained reconfigurable architectures or heterogeneous approaches need to be considered. Nanotechnology and Mixed-Signal architectures, and also the introduction of new communication architectures like Networks-on-Chip are the keywords for the design of Multiple Processor System on Chip (MPSoC). The question for the system designers is to choose the optimal granularity for the run-time reconfigurable hardware as well as for the processor IP cores. Introducing novel architectures always means to provide tools for industrial development. Tool-integration and supplier support, specification and verification are here the challenges to provide new technologies to the industry. The question is how new tools can be embedded into existing development methods and designflow? The purpose of this workshop is to evaluate strategies for future system design in reconfigurable hardwaresystem-architectures. Both aspects, hardware design and tool-integration into existing development tools will be discussed. Especially the novel trends in Mixed-Signal reconfigurable architectures are a main topic in this workshop. The main emphasis is on architectures, design-flow, tool-development, applications and system design. The workshop is targeted for hardware and system engineers as well as to researchers from academics and industry. ... Read more
S Ali, Southampton U, UK
2.3 New Directions in Analog Circuit Modelling
Tuesday, March 11 14:30-16:00, Room 03 (Speaker)
Petru Bacinschi, TU Darmstadt, DE
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Speaker)
M J Barragan, IMSE-CNM-CSIC, ES
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Juergen Becker, Karlsruhe Institute of Technology, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Organizer, Speaker)
Koen Bertels, TU Delft, NL
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Organizer, Speaker)
David M Binkley, U NC at Charlotte, US
D2 From Transistor to PLL - Analogue Design and EDA Methods
Monday, March 10 14:30-18:00, Room 11b (Organizer)
Emmanuel Blanc, Mentor Graphics, FR
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Speaker)
Philippe Bonnot, Thales Research and Technology, FR
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
A Bouali, Esterel, FR
7.1 The Future Car: Technology, Methods and Tools (Automotive Special Day)
Wednesday, March 12 16:30-18:00, Room 05 (Panelist)
Hans-Juergen Brand, Program Manager, AMD, DE
X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session)
Tuesday, March 11 15:45-16:45, Exhibition Theatre (Panelist)
Mark Dickinson, Altera Europe, UK
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
M Di Natale, Scuola S Anna Pisa, IT
7.1 The Future Car: Technology, Methods and Tools (Automotive Special Day)
Wednesday, March 12 16:30-18:00, Room 05 (Organizer)
A Doboli, State U of New York at Stony Brook, US
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Moderator)
Carsten Elgert, Mentor Graphics, DE
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Organizer)
Robert Esser, Xilinx Inc., IE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Luca Fanucci, Pisa U, IT
10.6 Analogue: How to Survive in the Era of Nano CMOS (Hot Topic)
Thursday, March 13 14:00-15:30, Room 12 (Moderator, Organizer)
H Fennel, Continental Teves, DE
7.1 The Future Car: Technology, Methods and Tools (Automotive Special Day)
Wednesday, March 12 16:30-18:00, Room 05 (Panelist)
Dietmar Fruehauf, Endress & Hauser GmbH, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Christian Gamrat, CEA Paris, FR
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Georges Gielen, KU Leuven, BE
10.6 Analogue: How to Survive in the Era of Nano CMOS (Hot Topic)
Thursday, March 13 14:00-15:30, Room 12 (Organizer)
D2 From Transistor to PLL - Analogue Design and EDA Methods
Monday, March 10 14:30-18:00, Room 11b (Speaker)
X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session)
Tuesday, March 11 15:45-16:45, Exhibition Theatre (Moderator)
M A Gourary, IPPM Russian Academy of Sciences, RU
3.3 Analog Simulation, Synthesis and Verification
Tuesday, March 11 16:30-18:00, Room 03 (Speaker)
Christoph Grimm, TU Vienna, AT
2.3 New Directions in Analog Circuit Modelling
Tuesday, March 11 14:30-16:00, Room 03 (Moderator)
Helmut Graeb, TU Munich, DE
3.3 Analog Simulation, Synthesis and Verification
Tuesday, March 11 16:30-18:00, Room 03 (Moderator)
D2 From Transistor to PLL - Analogue Design and EDA Methods
Monday, March 10 14:30-18:00, Room 11b (Speaker)
X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session)
Tuesday, March 11 15:45-16:45, Exhibition Theatre (Panelist)
Herbert Hanselmann, dSPACE GmbH, DE
7.1 The Future Car: Technology, Methods and Tools (Automotive Special Day)
Wednesday, March 12 16:30-18:00, Room 05 (Panelist)
Thomas Harms, Infineon, DE
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Speaker)
Walter Hartong, Cadence Design Systems GmbH, DE
X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session)
Tuesday, March 11 15:45-16:45, Exhibition Theatre (Panelist)
H Heinecke, BMW, DE
7.1 The Future Car: Technology, Methods and Tools (Automotive Special Day)
Wednesday, March 12 16:30-18:00, Room 05 (Panelist)
Volker Herbig, X-Fab, NN
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Speaker)
Paul Heysters, Recore Systems, NL
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Michael Huebner, Karlsruhe U, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Organizer)
Tom Kazmierski, Southampton U, UK
2.3 New Directions in Analog Circuit Modelling
Tuesday, March 11 14:30-16:00, Room 03 (Speaker)
3.3 Analog Simulation, Synthesis and Verification
Tuesday, March 11 16:30-18:00, Room 03 (Moderator)
H.G. Kerkhoff, Twente U, NL
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Moderator)
K Koch, Infineon Technologies, DE
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Speaker)
Herman Kopetz, TU Vienna, AT
7.1 The Future Car: Technology, Methods and Tools (Automotive Special Day)
Wednesday, March 12 16:30-18:00, Room 05 (Panelist)
J Machado Da Silva, INESC, PT
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Moderator)
Nicolas Mading, IBM Deutschland Entwicklung, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
T Massier, TU Munich, DE
2.3 New Directions in Analog Circuit Modelling
Tuesday, March 11 14:30-16:00, Room 03 (Speaker)
Heinz Mattes, Infineon Technologies, DE
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
M Momeni, TU Darmstadt, DE
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Speaker)
D Mueller, TU Munich, NN
2.3 New Directions in Analog Circuit Modelling
Tuesday, March 11 14:30-16:00, Room 03 (Moderator)
B Mulvaney, Freescale Semiconductor Inc, US
3.3 Analog Simulation, Synthesis and Verification
Tuesday, March 11 16:30-18:00, Room 03 (Speaker)
M Ortmanns, Freiburg U, NN
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Moderator)
Anton Ossner, Chartered Semiconductor, DE
E2 DfM in the Analogue and Digital World
Monday, March 10 14:30-18:00, Room 04a (Speaker)
Jose Pineda de Gyvez, NXP Semiconductors Research and TU Eindhoven, NL
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Ralf Popp, edacentrum GmbH, DE
X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session)
Tuesday, March 11 15:45-16:45, Exhibition Theatre (Organizer)
Peter Rotter, Infineon Technologies AG, DE
X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session)
Tuesday, March 11 15:45-16:45, Exhibition Theatre (Panelist)
Jaijeet Roychowdhury, U Minn Twin Cities, US
D2 From Transistor to PLL - Analogue Design and EDA Methods
Monday, March 10 14:30-18:00, Room 11b (Speaker)
Alberto L. Sangiovanni-Vincentelli, UC Berkeley, US
7.1 The Future Car: Technology, Methods and Tools (Automotive Special Day)
Wednesday, March 12 16:30-18:00, Room 05 (Moderator, Organizer)
Sebastian Sattler, Infineon Technologies, DE
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Frank Schenkel, MunEDA GmbH, DE
X3 Formal Methods to Verify Analog Circuit Design - Key or Phantasm? (Panel Session)
Tuesday, March 11 15:45-16:45, Exhibition Theatre (Panelist)
Eberhard Schueler, PACT, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
L Shun, Fudan U, CN
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Speaker)
Sebastian Steinhorst, Frankfurt/Main U, DE
3.3 Analog Simulation, Synthesis and Verification
Tuesday, March 11 16:30-18:00, Room 03 (Speaker)
H-G Stratigopoulos, TIMA Laboratory/CNRS, FR
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Yankin Tanurhan, Actel Corp., US
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
A Tchegho, TU Munich, DE
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Juergen Teich, Erlangen-Nuernberg U, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
Alexander Thomas, Karlsruhe U, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
I Vytyaz, Oregon State U, US
3.3 Analog Simulation, Synthesis and Verification
Tuesday, March 11 16:30-18:00, Room 03 (Speaker)
L Wang, Southampton U, UK
6.3 Robust Mixed-Signal System Design
Wednesday, March 12 14:30-16:00, Room 03 (Speaker)
Thomas Weber, Daimler, DE
7.1 The Future Car: Technology, Methods and Tools (Automotive Special Day)
Wednesday, March 12 16:30-18:00, Room 05 (Panelist)
Norbert Wehn, TU Kaiserslautern, DE
W1 Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures
Friday, March 14 8:45-16:30, Room 02 (Speaker)
A Zjajo, NXP Semiconductors, NL
1.5 Advances in BIST Techniques for Mixed-signal Devices
Tuesday, March 11 11:30-13:00, Room 11 (Speaker)
Analog experts call for new methodologies
SCD Source, Tets Maniwa, 08 February 2008
http://www.thkmail.com/email/lt/t_go.php?i=41&e=MjU3ODIx&l=-http--www.scdsource.com/article.php--Q-id--E-108
Business Forum Panel
Refining or re-defining the Analog Design Sign-Off Flow
DesignCon, Wednesday, February 6 2008 | 8:45 am -- 10:20 am
http://www.designcon.com/2008/conference/bf_wednesday.html
German R&D-Project VeronA covers the verification of analog circuits
edacentrum, February 2008
http://www.edacentrum.de/verona
DATE'08 Features European Research Projects
EDA Geek, February 15, 2008
http://edageek.com/2008/02/15/european-research/
European Research Projects Exhibit at DATE´08 ICM Munich
embedded computing, Germany 10 - 14 March, 2008
http://www.embedded-computing.com/news/db/?10348
DATE ist systemorientiert
Interview with Donatella Sciuto
elektroniknet, February 15, 2008
http://www.elektroniknet.de/home/designtools/news/n/d/date-ist-systemorientiert-1/
DATE 2008: Europa forscht gemeinsam an der EDA-Zukunft
elektroniknet, February 15, 2008
http://www.elektroniknet.de/home/designtools/news/n/d/date-2008-europa-forscht-gemeinsam-an-der-eda-zuk-1/
DATE 2008: EDA-Branche zu Gast in Muenchen
elektroniknet, February 15, 2008
http://www.elektroniknet.de/home/designtools/news/n/d/date-2008-eda-branche-zu-gast-in-muenchen-1/
DATE http://www.date-conference.com
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