Technical Programme Committee 2015

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Goto Track D: Design Methods and Tools

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Goto Track E: Embedded Systems Software

Track D: Design Methods and Tools

addressing design automation, design tools and hardware architectures for electronic and embedded systems. Emphasis is on methods, algorithms and tools related to the use of computers in designing complete systems. This includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows and environments.

Track Chair: David Atienza, EPFL, CH, Contact David Atienza

Topics

D1 System Specification and Modeling

Chair: Christian Haubelt, University of Rostock, DE, Contact Christian Haubelt

Co-Chair: Andy Pimentel, University of Amsterdam, NL, Contact Andy Pimentel

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Modeling and specification methodologies for complex HW-SW systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

D2 System Design, High-Level Synthesis and Optimization

Chair: Andreas Herkersdorf, Technische Universität München, DE, Contact Andreas Herkersdorf

Co-Chair: Nikil Dutt, University of California Irvine, US, Contact Nikil Dutt

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High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for hardware/software co-design and partitioning; control and data flow analysis; hardware/software interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation and binding techniques; multi-objective optimization techniques (performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; hw/sw design patterns for multi-core system on chip (MPSoC) and distributed, networked embedded systems; system-level design of heterogeneous computing systems.

D3 System Simulation and Validation

Chair: Prabhat Mishra, University of Florida, US, Contact Prabhat Mishra

Co-Chair: Elena Vatajelu, Politecnico de Torino, IT, Contact Elena Vatajelu

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Simulation-based verification; hardware/software co-simulation and validation; transaction-level validation; advanced simulation and emulation techniques from system to circuit level; simulation accelerators; testbench generation for functional validation; multi-domain simulation techniques; validation of cyber-physical systems, SoCs and emerging architectures.

D4 Formal Methods and System Verification

Chair: Jason Baumgartner, IBM, US, Contact Jason Baumgartner

Co-Chair: Julien Schmaltz, Eindhoven University of Technology, NL, Contact Julien Schmaltz

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Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction and decomposition techniques); technologies supporting formal verification; semi-formal verification techniques; formal verification of IPs, SoCs, cores, real-time and embedded systems; integration of verification into design flows; challenges of multi-cores, both as verification targets and as verification host platforms.

DT5 Design and Test for Analog and Mixed-Signal Systems and Circuits

Chair: Günhan Dündar, Boğaziçi University, TR, Contact Günhan Dündar

Co-Chair: Haralampos Stratigopoulos, TIMA Laboratory (CNRS - Univ. Grenoble Alpes), FR, Contact Haralampos Stratigopoulos

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Layout and topology generation; architecture and system synthesis; formal and symbolic techniques; hardware description languages for AMS circuits and systems; models of computation; innovative circuit topologies and architectures; modeling strategies for complex analogue, mixed signal or mixed-domain systems; self-healing and self- calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for- manufacturability and design-for-yield; test metrics and economics.

D6 Emerging Technologies and Systems

Chair: Michael Niemier, University Of Notre Dame, US, Contact Michael Niemier

Co-Chair: Ian O'Connor, University of Lyon, FR, Contact Ian O'Connor

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Modeling, circuit design, system architectures and design automation flows for future technologies: 3D integration, MEMS, non-CMOS logic, memory and interconnect, emerging FET devices, etc. System design methods and models of computation for emerging applications: lab-on-a-chip, biologically-based or -inspired computing systems, quantum computing, reversible logic, etc.

D7 Power Modeling, Optimization and Low-Power Design

Chair: Martino Ruggiero, EPFL, CH, Contact Martino Ruggiero

Co-Chair: Marisa Lopez-Vallejo, UPM, ES, Contact Marisa Lopez-Vallejo

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Algorithms, techniques and tools for power modeling, estimation and optimization of electronic systems applicable at all levels of the design, including both hardware and software; dynamic power management and leakage currents minimization; design flows and circuit architectures for ultra-low power consumption. Energy harvesting and battery modeling and design.

D8 Network on Chip

Chair: Fabien Clermidy, CEA-LETI, FR, Contact Fabien Clermidy

Co-Chair: Steven Nowick, Columbia, US, Contact Steven Nowick

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Architecture and modeling techniques for NoC; Design methodologies and architectures for on-chip interconnection networks: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security, power management and fault tolerance; Techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; Integration of external interfaces/memory controllers with NoCs; Cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; Programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

D9 Architectural and Microarchitectural Design

Chair: Todd Austin, University of Michigan, US, Contact Todd Austin

Co-Chair: Cristina Silvano, Politecnico di Milano, IT, Contact Cristina Silvano

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Architectural and micro-architectural design techniques, memory systems, power and energy efficient architectures, multi/many-core architectures, multi-threading techniques and support for parallelism, application-specific processors and accelerators, architectural support for reliability, security, timing predictability.

D10 Temperature and Variability Aware Design and Optimization

Chair: Siddharth Garg, U. Waterloo, CA, Contact Siddharth Garg

Co-Chair: Giovanni Ansaloni, EPFL, CH, Contact Giovanni Ansaloni

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The topic focuses on novel methods, techniques and architectures for counteracting variability of digital circuits and systems due to manufacturing, thermal or aging effects. Themes of interest include, but are not limited to, design and run-time thermal, variability and reliability management of SoCs and multi-core platforms (both at hardware and software level), as well as modeling and optimization approaches for manufacturing and temperature variations and degradation mechanisms in emerging 3D integration and manufacturing technologies.

D11 Reconfigurable Computing

Chair: Marco Platzner, University of Paderborn, DE, Contact Marco Platzner

Co-Chair: Ryan Kastner, University of California San Diego, US, Contact Ryan Kastner

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Statically and dynamically reconfigurable and reprogrammable systems and components: platforms and architectures, FPGAs, reconfigurable processors, design methods and tools for reconfigurable computing and communication systems.

D12 Logic and Physical Synthesis, Timing Analysis and Verification

Chair: José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact José Monteiro

Co-Chair: Patrick Groeneveld, Synopsys, US, Contact Patrick Groeneveld

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Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; state assignment; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; PLD and FPGA synthesis; arithmetic circuits; floorplanning; automatic place and route; interconnect- and performance-driven layout; process technology developments.

D13 On-Chip and Off-Chip Parasitic Extraction, Model Order Reduction and Signal Integrity

Chair: Luca Daniel, Massachusetts Institute of Technology, US, Contact Luca Daniel

Co-Chair: Luis Miguel Silveira, Technical University of Lisbon, PT, Contact Luis Miguel Silveira

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Parasitic and variation-aware extraction for on-chip interconnect, and passives (including RF inductors, substrate and power grids); Macro-modeling, behavioral and reduced order modeling; Electrical characterization, modeling and optimization of off-chip interconnects, TSVs and 3D interconnects, interposer and packaging; Modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate; Simulation and modeling for chip-package co-design, high-speed channels and equalizers.

Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, as well as innovative design and test methodologies, and applications of specific design and test technologies. Contributions should illustrate state-of-the-art or record-breaking designs, which will provide viable solutions in tomorrow's silicon and embedded systems. In topic A7, there is the opportunity to submit short, 2-page papers that relate to industrial research and practice.

Track Chair: Ayse Coskun, Boston University, US, Contact Ayse Coskun

Topics

A1 Green Computing Systems

Chair: Qinru Qiu, Syracuse University, US, Contact Qinru Qiu

Co-Chair: Andreas Burg, EPFL, CH, Contact Andreas Burg

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Application design experiences in industrial or academic projects with high industrial relevance or high environmental impact, targeting high performance or large-scale computing systems with a focus on energy efficiency. Target systems are massively parallel (super) computers, 2D/3D many-core systems, high performance computing clusters, data centers, cloud systems and cyber-physical systems. Topics of interest include, but are not limited to: software architectures for parallel systems and cloud computing, virtualization, energy-efficient memory, processor, or communication architectures, heterogeneous computing, resource management techniques including adaptive/learning-based methods, innovative data-center management strategies, big-data management, data centers powered by renewable energy sources, and data centers in the smart-grids.

A2 Communication, Consumer and Multimedia Systems

Chair: Theocharis Theocharides, Cyprus University, CY, Contact Theocharis Theocharides

Co-Chair: Sergio Saponara, University of Pisa, IT, Contact Sergio Saponara

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Practical design experience for communication, multimedia and consumer systems like smartphones, smart-books/tablets; examples are digital integrated circuits design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software-defined/cognitive radio systems; embedded systems design in the field of audio, video and computer vision domains; Application Specific Processors (ASP), Digital Signal Processors (DSP), Multi-Processor System on Chip (MPSoC) and Network on Chip (NoC) designs for these domains.

A3 Automotive Systems and Smart Energy Systems 

Chair: Bart Vermeulen, NXP Semiconductors, NL, Contact Bart Vermeulen

Co-Chair: David Boyle, Imperial College London, UK, Contact David Boyle

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This topic covers works that describe design experiences for automotive systems, smart energy systems, energy scavenging and harvesting for embedded systems, and related applications. This includes analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures, integrated sensors and transducers, RF architectures, in-vehicle networks, systems for electric vehicles, networks of systems (including car-to-car and car-to-infrastructure networks), and innovative concepts for power distribution, energy storage, and grid monitoring. Furthermore, this topic also includes design methods including models and tools, design of hardware and software components, architecture analysis and optimization, component-oriented design and system-level analysis and validation. Finally, topics of interest are also hardware and software solutions for run-time system management, including self-diagnostics and repair, energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems, and optimization of system energy efficiency.

A4 Ambient Intelligence and Ultra-Low Power Systems for Healthcare and Wellness

Chair: Srinivasan Murali, SmartCardia Sàrl, CH, Contact Srinivasan Murali

Co-Chair: Elisabeta Farella, Fondazione Bruno Kessler, IT, Contact Elisabeta Farella

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Medical, healthcare, and life science applications require increasingly smarter and smaller devices enabling to easily interact among each other, with the environment and with the users in a smooth and smart way. Personal and personalized medicine and rehabilitation is leading to a significant increase in both complex lab solutions as well as a myriad of consumer-like disposable devices. This topic covers the use of ambient intelligence, wireless body sensor networks and wearable technologies for healthcare, rehabilitation and wellness. This includes but it is not limited to: technologies for ultra-low/zero power systems for personal vital signs monitoring (such as heart rate, fitness devices); mobile system for motor rehabilitation and assessment; (bio)feedback system for rehabilitation and fitness based on wearable and mobile technologies; innovative implantable miniaturized sensors and actuators, personal health devices and assistive technology; Bio-MEMS; lab-on-a-chip; power management, on-board performance optimization and networking technologies for body area networks and ambient intelligence in wellness, healthcare and fitness.

A5 Secure Systems

Chair: Guido Bertoni, STMicroelectronics, IT, Contact Guido Bertoni

Co-Chair: Tim Güneysu, Ruhr University Bochum, DE, Contact Tim Güneysu

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Secured systems need a combination of hardware, software and embedded techniques to succeed. Indeed, the weakest link in the security chain determines the overall system security. This topic therefore invites papers on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random numbers generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including physically unclonable functions, and more.

A6 Reliable and Reconfigurable Systems

Chair: Marco Domenico Santambrogio, Polimi, IT, Contact Marco Domenico Santambrogio

Co-Chair: Praveen Raghavan, IMEC, BE, Contact Praveen Raghavan

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This topic covers the area of reliable and adaptive systems for practical applications. The scope of this topic includes, but not limited to, the development, optimization and practical application mechanisms to compensate for aging and temperature, development of fault-tolerant systems, redundant designs and applications, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

A7 Industrial Experiences Brief Papers

Chair: Ahmed Jerraya, CEA-LETI, FR, Contact Ahmed Jerraya

Co-Chair: Michael Nicolaidis, TIMA, Grenoble Institute of Technology, FR, Contact Michael Nicolaidis

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Short or long industrial papers with a minimum size of two pages, and up to six pages, are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.

Track T: Test and Robustness

covering all test, design-for-test, reliability and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analog and digital electronics. Including also diagnosis, failure mode analysis, debug and post-silicon validation challenges.

Track Chair: Cecilia Metra, University of Bologna, IT, cecilia [dot] metra at unibo [dot] it, phone: +390512093038

Topics

T1 Defects, Faults, Variability and Reliability Analysis and Modeling

Chair: Rob Aitken, ARM, US, Contact Rob Aitken

Co-Chair: Michel Renovell, LIRMM, FR, Contact Michel Renovell

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Identification, characterization and modeling of defects, faults and degradation mechanisms; defect-based fault analysis; reliability analysis and modeling, failure mode and effect analysis (FMEA) and physics of failures; noise and uncertainty modeling; test and reliability issues in emerging technologies; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations; process yield modeling and enhancement; design-for-manufacturability and design-for-yield.

T2 Test Generation, Simulation and Diagnosis

Chair: Bernd Becker, Universitaet Freiburg, DE, Contact Bernd Becker

Co-Chair: Jacob Abraham, UT Austin, US, Contact Jacob Abraham

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Test pattern generation (TPG); fault simulation; system test; test coverage metrics and estimation; adaptive test; self-healing/self-calibration/self-adaptation; diagnosis; debug; post-silicon validation; testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, 3D chips; hardware/software system test; processor based test.

T3 Design-for-Test, Test Compression and Access

Chair: Paolo Prinetto, Politecnico di Torino, IT, Contact Paolo Prinetto

Co-Chair: Magdy Abadir, Independent, US, Contact Magdy Abadir

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Design-for-test, built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DFT techniques, DFT for secure systems, DFT economics; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies, test economics.

T4 On-Line Test, Fault Tolerance and Robust Systems

Chair: Fabrizio Lombardi, Northeastern University, US, Contact Fabrizio Lombardi

Co-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact Cristiana Bolchini

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Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuit and system design; dependability evaluation, reliable system design; hardware/software recovery; self-repair; fault tolerance.

DT5 Design and Test for Analog and Mixed-Signal Systems and Circuits

Chair: Günhan Dündar, Boğaziçi University, TR, Contact Günhan Dündar

Co-Chair: Haralampos Stratigopoulos, TIMA Laboratory (CNRS - Univ. Grenoble Alpes), FR, Contact Haralampos Stratigopoulos

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Layout and topology generation; architecture and system synthesis; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.

Track E: Embedded Systems Software

is devoted to modelling, analysis, design and deployment of embedded software. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on modelbased design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked and dependable systems.

Track Chair: Lothar Thiele, ETH Zurich, CH, Contact Lothar Thiele

Topics

E1 Real-time, Networked, and Dependable Systems

Chair: Iain Bate, University of York, UK, Contact Iain Bate

Co-Chair: Rodolfo Pellizzoni, University of Waterloo, CA, Contact Rodolfo Pellizzoni

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Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; tools and design methods for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications

E2 Compilers for Embedded Systems

Chair: Alain Darte, ENS Lyon - INRIA, FR, Contact Alain Darte

Co-Chair: Rodric Rabbah, IBM Research, US, Contact Rodric Rabbah

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Compilers for embedded multi-core, heterogeneous, GPU, reconfigurable, or FPGA platforms; compiler-related tools for design space exploration, for iterative compilation, to complement HLS tools; just-in-time compilation and libraries for embedded and mobile devices; compiler support for enhanced debugging, profiling, and traceability; code analysis, optimization, and generation for different metrics (e.g., power, memory lifetime, WCET, etc.); compilation of domain specific or streaming languages for embedded systems; compilation tools for embedded systems as cloud services; certified compilers.

E3 Model-based Design and Verification for Embedded Systems

Chair: Saddek Bensalem, Université Joseph Fourier, FR, Contact Saddek Bensalem

Co-Chair: Linh Thi Xuan Phan, University of Pennsylvania, US, Contact Linh Thi Xuan Phan

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Verification techniques for embedded systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components.

E4 Embedded Software Architectures

Chair: Marc Geilen, Eindhoven University of Technology, NL, Contact Marc Geilen

Co-Chair: Frédéric Petrot, TIMA, Grenoble Institute of Technology, FR, Contact Frédéric Petrot

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Software architectures for MPSoC, multi/many-core and (GP)GPU-based systems; Programming paradigms and languages for embedded MPSoCs, multi/many-core and (GP)GPU-based systems; Virtualization and middleware for embedded systems, including resource-awareness, reconfiguration, safety and security aspects; Software support for reconfigurable components and accelerators; Software architectures for low power and temperature awareness

E5 Cyber-Physical Systems

Chair: Rolf Ernst, Technical University of Braunschweig, DE, Contact Rolf Ernst

Co-Chair: Paul Pop, Technical University of Denmark, DK, Contact Paul Pop

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Modeling, design, architecture, optimization, and analysis of Cyber-Physical Systems (CPS); Modeling techniques for large-scale cyber physical systems design and analysis; Verification and validation in CPS; Safety and cybersecurity in CPS systems; Internet of things and CPS: modeling, analysis, and design; Software-intensive CPS; Data-mining and CPS; Autonomous and semi-autonomous large-scale CPS and related issues; Socio-technical systems (ex. empowered consumer and organizational behavior in smart grids) and CPS; Cognitive control for CPS; Modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis; Case studies in CPS ranging from automotive systems, and avionics, to smart buildings and smart grids