UB-3.1 System Exploration with Software and Hardware
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P01 |
INSA Rennes - Jean-François Nezan, Pierre-Laurent Lagalaye PREESM - PREESM : an eclipse plug-in for the fast prototyping of signal processing applications PREESM is a fast prototyping tool for multicore architectures. The input are two graphs describing an algorithm and an architecture. It includes a generic graph editor, a graph transformation library and an automatic mapper/scheduler, simulation and code generation capabilities. |
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P02 |
Technological Institute of Piraeus - Dimitrios Marinos, Kimon Karras IO-MeMoS - Indoor diffused optical medical monitoring system A portable health-monitoring (ECG, blood pressure, Temperature, Resp. rate, Pulse oximetri) device for indoor environments, generating alerts for prevention of emergency cases. Data transmitted over an innovative wireless optical link allowing for security, no EM interference and high data rate. |
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P03 |
Technische Universität Braunschweig - Steffen Stein, Moritz Neukirchner EPOC - EPOC Contracting Framework, Self-Configuration of evolving hard-real time systems We present a runtime solution to self-configuration of real-time systems undergoing an evolution. To achieve this, we extended the EPOC Framework by a distributed constraint solving algorithm that finds feasible priority assignments in SPP scheduled systems taking end-to-end latencies into account. |
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P04 |
National Technical University of Athens - Dimitrios Soudris, Sotirios Xydis, Alex Bartzas MTh-DMM-Explorer - Dynamic Memory Management Customization for Multi-Processor Systems-on-Chip The MTh-DMM-Explorer: It models the complete design space of dynamic memory managers for MPSoCs in decision trees, performs automated exploration (In the inter-thread design space and in the intra-thread design space based on the constraints generated from the previous step). It automatically generate the source code of Pareto-optimal customized dynamic memory managers. |
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P05 |
National Chung Cheng University - Jih-Sheng Shen, Pao-Ann Hsiung PRESSNoC - Power-Aware and Reliable Encoding Schemes Supported Reconfigurable Network-on-Chip Architecture To meet the varying run-time requirements of Network-on-Chip (NoC) communication on reliability and power-efficiency, we propose a Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture. |
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P06 |
Technische Universität Braunschweig - Harald Schrom Embedded system for Building Management with Timing Verification We demonstrate a Building Management System with small-scale devices, low energy consumption and Timing Verification for the use in “Smart Buildings” and a concept for its Timing verification to guarantee the correct timing of the networked real-time electronic components and their interaction. |
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P07 |
University College London - Yiannis Andreopoulos, Davide Anastasia ORIP - Operational Refinement of Multimedia Processing A live video capturing and processing system is presented on a state-of-the-art low-power device (xo-laptop or “100$ laptop). We demonstrate how we can change quality/complexity on-the-fly while capturing and processing, thereby allowing for joint quality/throughput/power-consumption tradeoffs. |
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P08 |
ad-hoc presentation |
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P09 |
University of Tehran - Fatemeh Asgari, Hasan Sohofi, Vahide Akhlaghi Migrating from RTL to ESL via SystemC Training We are presenting a training package for describing hardware with C++ and SystemC. The package contains videos, reading materials, slides, and software. After covering the basics, we start at the RT level with a section on VHDL. This is followed by a corresponding SystemC presentation, and then moving up into SystemC channels. The package readies an RTL designer for advanced ESL designs. SystemC simulation software and RTL translation tools are included in this package. |
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P10 |
University of Tehran - Mahshid Sedghi Ghozloocheh, Fatemeh Javaheri, Nastaran Nemati ESL Design Methodology for Architecture Exploration using OSCI TLM 2.0 Standard We present a methodology for design of complex digital systems at system level through a training video. We have implemented a variety of designs using OSCI TLM 2.0 standard in order to come up with the design methodology. The video explains a number of design sub-levels and guidelines for design at each sub-level. |
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P11 |
TU Vienna - Markus Damm, Stefan Mahlknecht, Christoph Grimm SmartCoDe - Smart Contol of Demand The objective is to investigate means and architectures that allow integration of (RF) communication, and switching and managing of high-volgate (230V) in a System-in-Package (SiP) which is funded in the FP7 project SmartCoDe. As a result, the power consumption of households and environments shall be reduced and become planable ("demand-side management"). |
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P12 |
ad-hoc presentation |
