UB-1.5 Robust Design Environments
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P01 |
National Technical University of Athens - Kostas Siozios A High-Level Tool Framework for Exploring and Designing NoC Architectures for 3D Ics This high-level tool framework supports the exploration of alternative NoC architectures targeting to 3D ICs, in terms of numerous design parameters (i.e. energy dissipation, latency, QoS, etc) under multiple topologies. Also, it automates the generation of RTL description for the optimized 3D NoC topology. |
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P02 |
Fraunhofer - Tanja Clees, Bernhard Klaassen MECS, DesParO - Hierarchical Simulation and Robust Design Aspects Within a Fraunhofer research project we are developing a hierarchical simulation strategy and accompanying software modules with special emphasis on easy transfer between design levels, investigation of the influence of parameter changes over several levels, and general robust design aspects. |
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P03 |
Carnegie Mellon University - Kai-Chiang Wu Reducing Circuit Soft Error Rate (SER): From Combinational to Sequential Circuits Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits. The framework to be demonstrated aims at reducing the circuit susceptibility to soft errors, quantified as soft error rate (SER). Three methods, which target different parts of logic circuits, are developed for SER reduction of both combinational and sequential circuits. |
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P04 |
Technische Universität Braunschweig - Harald Schrom Embedded system for Building Management with Timing Verification We demonstrate a Building Management System with small-scale devices, low energy consumption and Timing Verification for the use in “Smart Buildings” and a concept for its Timing verification to guarantee the correct timing of the networked real-time electronic components and their interaction. |
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P05 |
Tallinn University of Technology - Maksim Jenihhin, Anton Chepurov, Jaan Raik ZamiaCAD - Simulator for ZamiaCAD Integrated Hardware Design Environment We present a simulator component for ZamiaCAD which is an environment for hardware design entry, analysis, integration and simulation. ZamiaCAD can handle large industrial designs such as the state-of-the-art processors from IBM. It is implemented as a plug-in for the open source Eclipse IDE. |
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P06 |
Dresden University of Technology - Ute Schiffel, André Schmitt SEP - Software Encoded Processing – Enable Software to Detect Execution Errors Software Encoded Processing transforms software from an unsafe original to a safe version. The functionality of both versions is equivalent. But while the unsafe original version is vulnerable to execution errors such as transient and permanent hardware errors, the safe version is not. |
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P07 |
IMMS - Komla Amenyo Agla SL2HW-Demo - From SystemC to real hardware - SystemC FPGA design flow for a microcontroller based temperature measurement system A complete design flow of digital circuit components from a SystemC description up to implementation in hardware (FPGA) included embedded software algorithm is shown. The design is an example of temperature measurement and analysis based on a sensor with a SPI-Interface and a RISC Microcontroller. |
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P08 |
Federal University UFRGS - Vinicius Callegaro SwitchCraft - SwitchCraft – a tool for generation of switch networks for digital cells SwitchCraft environment provides a set of tools for switch network generation. Different CMOS logic styles can be targeted. Transistor networks can be generated from Boolean equations and/or from BDDs. Auxiliary tools are also provided for network profile data, power estimators, schematic viewer. |
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P09 |
University of Applied Science Offenburg - Daniel Bau, Andreas Kreker studPOD - studPOD: Student Digital Assistant with own OS and own SIRIUS processor core in FPGA and fully integrated in 0.18 uCMOS Development environment with Editor, C-Compiler, Simulator for application development on the studPOD in High level language C. |
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P10 |
University of Tehran - Nastaran Nemati, Majid Namaki-Shoushtari, Paria Najafi-Haghi A Package for Test Hardware Evaluation In this work, a test hardware evaluation package based on Verilog and its procedural interface is presented. This package contains components like test insertion, fault simulation, etc, and its focus is on DFT and BIST evaluation and determining their necessity. |
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P11 |
ad-hoc presentation |
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P12 |
ad-hoc presentation |
