W5 3D Integration - Applications, Technology, Architechture, Design, Automation, and Test

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Session Type: 
workshop
Date: 
Fri, 2012-03-16
Time: 
TBD
Location / Room: 
TBD

Organisers:

Sandeep Kumar Goel General Chair
TSMC
2585 Junction Avenue,
San Jose, CA 95134
E-mail: skgoelattsmc [dot] com
Qiang Xu Program Co-Chair
The Chinese University of Hong Kong
Room 1008, Ho Sin Hang Building,
Shatin, N.T., Hong Kong
E-mail: qxuatcse [dot] cuhk [dot] edu [dot] hk
Saqib Khursheed Program Co-Chair
University of Southampton
Room 4221, Building 59, School of ECS,
SO17 1BJ, Southampton, UK
E-mail: sskatecs [dot] soton [dot] ac [dot] uk

Description:

3D Integration is a promising technology for extending Moore's momentum in the next decennium, offering heterogeneous technology integration, higher transistor density, faster interconnects, and potentially lower cost and time-to-market. To produce 3D chips, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.

The last three editions of this workshop took place in conjunction with DATE 2009 to DATE 2011.

Nice, FranceDresden, GermanyGrenoble, France

The call for papers (CFP) for the upcoming workshop to be held in conjunction with DATE 2012 is available here.

Topic Areas

You are invited to participate and submit your contributions to the DATE 2012 Friday Workshop on 3D Integration. The areas of interest include (but are not limited to) the following topics:

  • 3D technologies: chip-on-chip, micro-bumping, contactless, and through-silicon-vias interconnect
  • TSV formation, perm./temp. wafer (de-)bonding
  • 3D architectures and design space exploration
  • 3D combinations of logic, memory, analog, RF
  • Application, product, or test chip case studies
  • 3D design methods and EDA tools
  • Signal and power integrity, and ESD in 3D
  • Thermo(-mechanical) analysis and -aware design
  • Chip-package co-design for 3D
  • Test, design-for-test, and debug techniques for 3D
  • Wafer test access, KGD test, thin-wafer handling
  • Economic benefit/cost trade-off studies
  • Standardization initiatives

Submission Instructions

Submissions are invited in the form of (extended) abstracts not exceeding two pages and must be sent in as PDF file to <qxuatcse [dot] cuhk [dot] edu [dot] hk> and <sskatecs [dot] soton [dot] ac [dot] uk> with "DATE12-3D-WS" as subject. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, and technical soundness. Selected submissions can be accepted for regular or poster presentation. At the workshop, an Electronic Workshop Digest will be made available to all workshop participants, which will include all material that authors are willing to provide: abstract, paper, slides, poster, etc.

Paper Submission deadlineDecember 11, 2011
Notification of AcceptanceDecember 19, 2011
Camera-Ready Material due dateFebruary 25, 2012
Groups: