We are happy to announce that the University Booth programme for DATE 2011 is now available. Please take a look at the programme to see more information abotu the demonstrations at the University Booth in Grenoble. This year, there will be more than 50 different demonstrations presented during the three days exhibition. In the next weeks we will add more information about the demonstrations. So please visit again the University Booth website to see the latest news.

Lorena Anghel and Volker Schöber

University Booth Programme 2011

Tuesday 15th March

10h30-12h30

• SCoPE - SystemC Cosimulation and Performance Estimation. Application to Power and Thermal Aware Design, Daniel Calvo, University of Cantabria, Spain
• A dynamically reconfigurable many-core platform for streaming applications, Timon Ter Braak, University of Twente, Netherlands
• Embedded Instruments for Board-level Test, Igor Aleksejev, Tallinn University of Technology, Estonia
• FIFA - A Fault-Injection-Fault-Analysis-based tool for reliability assessment at RTL level, Gutemberg Goncalves dos Santos Junior, Telecom Paristech / EDF R&D, France
• Monitoring and Control of a Dynamically Reconfigurable Wireless Sensor Node Powered by Hybrid Energy Harvesting, François Philipp, TU Darmstadt, Germany
• Integrated System for Automatic Personal Identification and Indoor Localization and Tracking, Luigi Pomante, University of L'Aquila, Italy
• zamiaCAD - Open source platform for advanced hardware design, Maksim Jenihhin, Tallinn University of Technology, Estonia
• A platform for the simulation of  radiation effects on processors by fault injection, Raoul Velazco, TIMA, France
• RobuCheck - A Formal Verification Tool for Fault Tolerant Systems, Stefan Frehse, University of Bremen, Germany
• Structured Layout Generation Tool for Analog Circuits, BoYang, The University of Kitakyushu, Japan
• Demonstration of a Coverage Driven Verification Environment for UML Models of Systems-on-Chip, Daniel Knorreck, Telecom ParisTech, France

12h30-14h30

• A dynamically reconfigurable many-core platform for streaming applications, Timon Ter Braak, University of Twente, Netherlands
• UTLEON3 - an extended SPARC v8 with microthreading, Martin Danek, UTIA AV CR, v.v.i., Czech Republic
• Biological Information Sensing Systems, Sho Ninomiya, Osaka University, Japan
• A platform for the simulation of  radiation effects on processors by fault injection, Raoul Velazco, TIMA, France
• Demonstration of a Coverage Driven Verification Environment for UML Models of Systems-on-Chip, Daniel Knorreck, Telecom ParisTech, France
• SYNTHORUS - Fast Prototyping from Assertions, Katell Morin-Allory, TIMA, France

14h30-16h30

• Optimization of MP-SoC Middleware for event-driven dynamic Applications , Dirk Stroobandt, Ghent University, Belgium
• A dynamically reconfigurable many-core platform for streaming applications, Timon Ter Braak, University of Twente, Netherlands
• PowerMixer-IP - Power Analysis Framwork for SoC Designs, Chia-Chien Weng, National Tsing Hua University, Taiwan (Republic of China)
• A simulation framework for the assessment of NBTI-induced aging effects in SoC designs, Andrea Calimera, Politecnico di Torino, Italy
• Hierarchical Test Application and Evaluation, Fatemeh Javaheri, University of Tehran, Iran
• Functional Hardware Design in C?aSH, Christiaan Baaij, University of Twente, Netherlands
• RevKit - A Toolkit for Reversible Circuit Design, Robert Wille, University of Bremen, Germany
• RobuCheck - A Formal Verification Tool for Fault Tolerant Systems, Stefan Frehse, University of Bremen, Germany
• Sigma-Delta Converter Self-calibration using a BIST function, Matthieu Dubois, TIMA, France
• Hierarchical Simulation and Robust Design Aspects, Bernhard Klaassen, Fraunhofer Institute SCAI, Germany

16h30-18h30

• SCoPE - SystemC Cosimulation and Performance Estimation. Application to Power and Thermal Aware Design, Daniel Calvo, University of Cantabria, Spain
• HDL-based Test Evaluation Tool Set, Majid Namaki-Shoushtari, University of Tehran, Iran
• Functional Hardware Design in C?aSH, Christiaan Baaij, University of Twente, Netherlands
• Open-PEOPLE - Open - Power and Energy Optimization Platform and Estimator, Jeremie Guillot, LabSTICC, France
• PSL-Based Verification of SystemC TLM Designs, Laurence PIERRE, TIMA, France
• Optimizing memory testing architectures: the Memory Bist Optimizer, Yann Kieffer, laboratoire G-SCOP, France

Wednesday, March 16th

10h00-12h30

• ATLAS - A Framework for NoC Generation and Evaluation, Aline Vieira de Mello, LIP6, France
• IFPEC -. Integrated Framework for Processor Extension Generation and Application Compilation, Christophe Wolinski, ESIR / IRISA, France
• EDA tools for soft error tolerance, Masayoshi Yoshimura, Kyushu University, Japan
• The GeCos compiler infrastructure, STEVEN DERRIEN, University of Rennes1 , France
• Biological Information Sensing Systems, Sho Ninomiya, Osaka University, Japan
• HDL-based Test Evaluation Tool Set, Majid Namaki-Shoushtari, University of Tehran, Iran
• Hierarchical Test Application and Evaluation, FatemehJ avaheri, University of Tehran, Iran
• A Software Supported Methodology for Rapid Exploration of Memory Hierarchies in FPGAs, Harry Sidiropoulos, National Technical University of Athens, Greece
• Monitoring and Control of a Dynamically Reconfigurable Wireless Sensor Node Powered by Hybrid Energy Harvesting, François Philipp, TU Darmstadt, Germany
• Creative Circuit Design Solutions (CREDO), Matthias Mielke, University of Siegen, Germany
• zamiaCAD - Open source platform for advanced hardware design, Maksim Jenihhin, Tallinn University of Technology, Estonia
• SYNTHORUS - Fast Prototyping from Assertions, Katell Morin-Allory, TIMA, France

12h30-14h30

• A dynamically reconfigurable many-core platform for streaming applications, Timon Ter Braak, University of Twente, Netherlands
• IFPEC - Integrated Framework for Processor Extension Generation and Application Compilation, Christophe Wolinski, ESIR / IRISA, France
• EDA tools for soft error tolerance, Masayoshi Yoshimura, ESIR / IRISA, France
• The GeCos compiler infrastructure, STEVEN DERRIEN, ESIR / IRISA, France
• Compiler Assisted Energy Reduction Techniques for Embedded Processors, Tohru Ishihara, Kyushu University, Japan
• ID.Fix - Infrastructure for the design of fixed-point systems, Daniel MENARD, IRISA - INRIA, France
• UTIA master-worker platform with resource management, Zdenek Pohl, UTIA AV CR, v.v.i., Czech Republic
• UTLEON3 - an extended SPARC v8 with microthreading, Martin Danek, UTIA AV CR, v.v.i., Czech Republic
• FPGA Prototype of Flexible Heterogeneous multi-ASIP NoC-based Uni?ed Turbo Receiver, Amer Baghdadi, Telecom Bretagne, France
• On Taming Graphical Modeling - The KIELER Eclipse Project, Reinhard von Hanxleden, Kiel University, Germany
• Demonstration of a Coverage Driven Verification Environment for UML Models of Systems-on-Chip, Daniel Knorreck, Telecom ParisTech, France

14h30-16h30

• Compiler Assisted Energy Reduction Techniques for Embedded Processors, Tohru Ishihara, TIMA, France
• UTIA master-worker platform with resource management, Zdenek Pohl, UTIA AV CR, v.v.i., Czech Republic
• Biological Information Sensing Systems, ShoNinomiya, Osaka University, Japan
• Magnetic Process Design Kit for Hybrid CMOS / Magnetic process, GREGORYDI PENDINA, CMP, France
• FPGA Prototype of Flexible Heterogeneous multi-ASIP NoC-based Uni?ed Turbo Receiver, Amer Baghdadi, Telecom Bretagne, France
• All-Digital PLL Compiler for On-Chip High-Speed Clock Generation, Chao-Wen Tzeng, National Tsing Hua University, Taiwan, Taiwan (Republic of China)
• RevKit - A Toolkit for Reversible Circuit Design, Robert Wille, University of Bremen, Germany
• ASIP Design in the Lissom Project, KarelMasarik, Brno University of Technology, Czech Republic
• A platform for the simulation of  radiation effects on processors by fault injection, Raoul Velazco, TIMA, France
• On Taming Graphical Modeling - The KIELER Eclipse Project, Reinhard von Hanxleden, Kiel University, Germany
• Open-PEOPLE - Open - Power and Energy Optimization Platform and Estimator, Jeremie Guillot, LabSTICC, France
• PSL-Based Verification of SystemC TLM Designs, Laurence PIERRE, TIMA, France

16h30-18h30

• Optimization of MP-SoC Middleware for event-driven dynamic Applications , Dirk Stroobandt, Ghent University, Belgium
• SCoPE-  SystemC Cosimulation and Performance Estimation. Application to Power and Thermal Aware Design, Daniel Calvo, University of Cantabria, Spain
• ID.Fix - Infrastructure for the design of fixed-point systems, Daniel MENARD, IRISA - INRIA, France
• UTIA master-worker platform with resource management, Zdenek Pohl, UTIA AV CR, v.v.i., Czech Republic
• FPGA Prototype of Flexible Heterogeneous multi-ASIP NoC-based Uni?ed Turbo Receiver, Amer Baghdadi, Telecom Bretagne, France
• Daedalus - The System-Level Design Flow for Heterogenous MPSoC platforms, Jiali Teddy ZHAI, Unversity Leiden, Netherlands
• EduCAD - an Efficient, Flexible and Easily Revisable Physical Design Tool for Educational Purposes, Saba Amanollahi, SBU, Iran
• A platform for the simulation of  radiation effects on processors by fault injection, Raoul Velazco, TIMA, France
• On Taming Graphical Modeling - The KIELER Eclipse Project, Reinhard von Hanxleden, Kiel University, Germany
• PSL-Based Verification of SystemC TLM Designs, Laurence PIERRE, TIMA, France

Thursday, March 17th
10h00-12h00

• Embedded Instruments for Board-level Test, Igor Aleksejev, University of L'Aquila, Italy
• UTIA master-worker platform with resource management, Zdenek  Pohl, UTIA AV CR, v.v.i., Czech Republic
• EduCAD - an Efficient, Flexible and Easily Revisable Physical Design Tool for Educational Purposes, Saba Amanollahi, SBU, Iran
• VOCIS - A Versatile Simulation model for On-chip interconnect fault tolerance and performance, Fabien Chaix, TIMA, France
• A platform for the simulation of  radiation effects on processors by fault injection, Raoul Velazco, TIMA, France
• RobuCheck - A Formal Verification Tool for Fault Tolerant Systems , Stefan Frehse, University of Bremen, Germany
• Sigma-Delta Converter Self-calibration using a BIST function, Matthieu Dubois, TIMA, France
• HexaPus - emulating parallel embedded systems, Stephane Mancini, TIMA, France
• PSL-Based Verification of SystemC TLM Designs, Laurence PIERRE, TIMA, France
• Optimizing memory testing architectures: the Memory Bist Optimizer, Yann Kieffer, laboratoire G-SCOP, France
• SYNTHORUS - Fast Prototyping from Assertions, Katell Morin-Allory, TIMA, France

12h00-14h00

• A dynamically reconfigurable many-core platform for streaming applications, Timon Ter Braak, University of Twente, Netherlands
• UTIA master-worker platform with resource management, Zdenek Pohl, UTIA AV CR, v.v.i., Czech Republic
• UTLEON3 - an extended SPARC v8 with microthreading, Martin Danek, UTIA AV CR, v.v.i., Czech Republic
• Statistical Thermal Evaluation and Yield Improvement Considering Process Variation for 3D Chip-Multiprocessors, Da-Cheng Juan, Carnegie Mellon University, USA
• Functional Hardware Design in C?aSH, Christiaan Baaij, University of Twente, Netherlands
• Daedalus - The System-Level Design Flow for Heterogenous MPSoC platforms, Jiali Teddy ZHAI, Unversity Leiden, Netherlands
• Creative Circuit Design Solutions (CREDO), Matthias Mielke, University of Siegen, Germany
• VOCIS: A Versatile Simulation model for On-chip interconnect fault tolerance and performance, Fabien Chaix, TIMA, France
• PSL-Based Verification of SystemC TLM Designs, Laurence PIERRE, TIMA, France
• SYNTHORUS : Fast Prototyping from Assertions, Katell Morin-Allory, TIMA, France

14h00-16h00

• Optimization of MP-SoC Middleware for event-driven dynamic Applications , Dirk Stroobandt, Ghent University, Belgium
• SCoPE - SystemC Cosimulation and Performance Estimation. Application to Power and Thermal Aware Design, Daniel Calvo, University of Cantabria, Spain
• Statistical Thermal Evaluation and Yield Improvement Considering Process Variation for 3D Chip-Multiprocessors, Da-Cheng Juan, Carnegie Mellon University, USA
• Magnetic Process Design Kit for Hybrid CMOS / Magnetic process, GREGORY DI PENDINA, CMP, France
• Functional Hardware Design in C?aSH, Christiaan Baaij, University of Twente, Netherlands
• RevKit - A Toolkit for Reversible Circuit Design, Robert Wille, University of Bremen, Germany