Erik Jan Marinissen, IMEC, BE
Yann Guillou, ST-Ericsson, FR
Geert Van der Plas, IMEC, BE
|0830-1000||SESSION 1: OPENING|
Moderator: Peter Schneider - Fraunhofer Institute, DE
"What We Have Learned From SOC Is What Is Driving 3D Integration"
Cheng-Wen Wu - ICL, ITRI, TW / National Tsing-Hua Univ., TW
One of the most serious issues that IC developers face today is the development cost of a typical system-on-chip (SOC) using state-of-the-art technology - tens of million dollars for a case, and the cost continues to soar with the ever innovating technology. Today, more and more people are looking for alternative solutions, and three-dimensional (3D) integration is a feasible one that provides better or equal performance with lower cost, especially the development cost. Stacking dies using the Through-Silicon-Via (TSV) technology has been considered one of the most promising solutions to extending the life of Moore's Law in semiconductor industry, but of course there are problems to be solved before the infrastructure can be set up to support the industry for manufacturing TSV-based 3D integrated devices. In this talk we will discuss the design and test issues, and possible solutions for 3D integrated devices. Specifically, stacked dies will face the severe problem of exponential decay rate in their quality if the currently employed post-bond testing is not changed. We will propose a practical test methodology for wafer-on-wafer and die-on-wafer 3D integration, which is a solution extended from our SOC test methodology. Our approach allows die test before bonding, TSV test for vertical interconnect verification, as well as die test in all layers of the stack after bonding.
"OSAT - Role as Partner in 3D Integration"
ChoonHeung Lee - Amkor Technology, KR
Outsourced semiconductor assembly and test (OSAT) providers have developed and scaled up new technologies for 3D integration over the past decade to become a strategic partner to semiconductor suppliers across the globe. OSAT capabilities have been critical to the industry in delivering the billions of stacked die and stacked package technologies that have been critical components for a wide range of mobile and high-performance applications to date. Now OSAT providers are working closely with their semiconductor suppliers to develop the technologies and capacities required to support a wide range of new 3D integration requirements utilizing TSV interconnects and flip-chip on flip-chip stacked structures. This talk will summarize various TSV supply chain flows and technologies OSAT providers are developing in partnership with customers, outline the critical TSV wafer processing and package assembly requirements OSAT providers must support, and summarize the TSV technology development status within OSAT industry leader Amkor Technology.
|1000-1030||SESSION 2: POSTERS|
Posters (see below) - coffee + tea break
|1030-1200||SESSION 3: PAPERS|
Moderator: Herb Reiter - Eda2Asic, USA
|1030||3D-PIC: An Error-Tolerant 3D CMOS Imager,|
Hsiu-Ming (Sherman) Chang, Kwang-Ting (Tim) Cheng - UC Santa Barbara, USA; Jiun-Lang Huang - Natl. Taiwan Univ., TW; Ding-Ming Kwai - ITRI, TW; Cheng-Wen Wu - ITRI, TW / Natl. Tsing-Hua Univ., TW
|1100||An Analytical Study on the Role of Thermal TSVs in a 3D-IC Chip Stack,|
Min Ni, Qing Su, Zongwu Tang, Jamil Kawa - Synopsys, US
|1130||A Novel NOC Architecture Framework for 3D Chip MPSoC Implementations,|
Konstantinos Tatas, Costas Kyriacou - Frederick Univ., Cyprus; Alexandros Bartzas, Kostas Siozios, Dimitrios Soudris - Natl. Techn. Univ. of Athens, GR
|1300-1430||SESSION 4: PAPERS|
Moderator: Stojan Kanev - Cascade Microtech, DE
|1300||High Aspect-Ratio Through-Silicon Vias: How Molecular Engineering Impacts the 3D-IC Design Space,|
Claudio Truzzi, Frederic Raynal, Vincent Mevellec - Alchimer, FR
|1330||Debonding of Temporary Bonded Wafers with Topography for 3D Integration,|
Peter Bisson, Sumant Sood, Jim Hermanowski, Wilfried Bair - Suss MicroTech, US
|1400||Modeling TSV Open Defects in Three-Dimensional Memory,|
Li Jiang, Yuxi Liu, Qiang Xu - Chinese Univ. of Hong-Kong, HK
|1430-1500||SESSION 5: POSTERS|
Posters (see below) - coffee + tea break
SESSION 6: PANEL DISCUSSION
POSTER SESSIONS 2 and 5 POSTERS
1000-1030h and 1430-1500h
Please find here the Call for Participation.
Please find here the Electronic Workshop Digest (~ 50 MB, Version 2: March 30, 2010)
The Design, Automation, and Test in Europe conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. The conference includes plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days, and a track for executives. Friday Workshops are focusing on emerging research and application topics. At DATE 2010, one of the Friday Workshops is devoted to 3D Integration. This one-day event consists of two invited keynote addresses, regular and poster presentations, and a panel session.
3D Integration is a promising technology for extending Moore’s momentum in the next decennium, offering heterogeneous technology integration, higher transistor density, faster interconnects, and potentially lower cost and time-to-market. But in order to produce 3D chips, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges. The first edition of this workshop took place in conjunction with DATE 2009 (see http://www.date-conference.com/date09/conference/workshop-w5).
The workshop program contains the following elements.
Two invited keynote addresses
For the detailed version of the program, please see below.
PARTICIPATION and REGISTRATION
You are invited to participate in the workshop. Participation requires registration and a registration fee. Registration will be available through the DATE’10 web site, as well as on-site in Dresden, Germany. Check the DATE web site (http://www.date-conference.com) for rates and other information. Workshop registration includes luncheon, coffee breaks, and download access to the Electronic Workshop Digest, containing extended abstracts, papers, slides, posters.
OTHER 3D INTEGRATION ACTIVITIES DURING DATE WEEK
Erik Jan Marinissen – General Chair
3001 Leuven, Belgium
E-mail: erik [dot] jan [dot] marinissen [at] imec [dot] be
Yann Guillou – Program Co-Chair
12, rue Jules Horowitz – BP 217
38019 Grenoble cedex, France
E-mail: yann [dot] guillou [at] stericsson [dot] com
Geert Van der Plas – Program Co-Chair
3001 Leuven, Belgium
E-mail: geert [dot] vanderplas [at] imec [dot] be