| Tue, 2009-04-21 | 1.1 | PLENARY: OPENING AND KEYNOTE | 08:40 - 10:30 | Athena, Level 2 | Read More | plenary session |
| Tue, 2009-04-21 | 2.1 | EXECUTIVE SESSION – FPGA Developments: What is New? | 11:30 - 13:00 | Hermes, Level 2 | Read More | executive panel session |
| Tue, 2009-04-21 | 2.2 | Emerging Interconnection Technologies for Multicore | 11:30 - 13:00 | Clio, Level 3 | Read More | technical session |
| Tue, 2009-04-21 | 2.3 | Applications on Reconfigurable Hardware 1 | 11:30 - 13:00 | Gallieni 3, Level 2 | Read More | technical session |
| Tue, 2009-04-21 | 2.4 | Task Allocation for MPSoCs | 11:30 - 13:00 | Thalie, Level 3 | Read More | technical session |
| Tue, 2009-04-21 | 2.5 | Advanced Approaches for Reliability Improvement | 11:30 - 13:00 | Erato, Level 3 | Read More | technical session |
| Tue, 2009-04-21 | 2.6 | Scheduling and Timing Analysis for Embedded Real-Time Systems | 11:30 - 13:00 | Uranie, Level 3 | Read More | technical session |
| Tue, 2009-04-21 | 2.7 | System-Level Synthesis and Optimisation | 11:30 - 13:00 | Gallieni AB, Level 2 | Read More | technical session |
| Tue, 2009-04-21 | 2.8 | PANEL SESSION – Consolidation, a Modern “Moor of Venice” Tale | 11:30 - 13:00 | Exhibition Theatre, Level 2 | Read More | technical session | panel session |
| Tue, 2009-04-21 | 3.1 | EXECUTIVE SESSION – Are We There Yet? A Progress Report on the Move to 32nm | 14:30 - 16:00 | Hermes, Level 2 | Read More | executive panel session |
