Description:
FMGALS'09 is the 4th edition in a series of bi-annual workshops held in Pisa in 2003 (in conjunction with FME'03), in Verona in 2005 and Nice in 2007 (in conjunction with MEMOCODE'05 and MEMOCODE'07). Past workshop proceedings have been published with Elsevier's Electronic Notes in Theoretical Computer Science (ENTCS). Special issues of the Springer Journal Formal Methods in System Design and of the IEEE Design and Test magazine have been edited including most influential contributions to the workshop. The goals of the workshop is to bring together researchers and practitioners of all  aspects of GALS architecture including, but not limited to, models of computation, formal methods, modeling frameworks and tools, formal verification techniques, design automation, experimental results and case studies.

Increasing number of cores and clock speed coupled with the decreasing feature sizes of semiconductor technology, synchronous designs run by a single clock implies difficulties with clock distribution and excessive power consumptions. For this reason, the Globally Asynchronous Locally Synchronous (GALS) model of computation has emerged as the paradigm of choice for SoC design with multiple timing domains.  At the same time, embedded software is run on multiple processors distributed over an asynchronous communication infrastructure (such as CAN or FlexRay bus in automotive). Due to the inherent subtleties of asynchronous communication of synchronous components, formal methods are vital to make the GALS paradigm a success. The FMGALS workshop aims at bringing together researchers from different communities interested in GALS design, and in applying formal methods in creating CAD tools enabling correct by construction GALS design.

The programme of FMGALS’09 will be based on peer-reviewed papers selected from submissions open to any one contributing new research results, case studies, and methodology papers in one of the following topics: 

• Formal design and synthesis techniques for GALS
• GALS model of computation for software architectures
• Architectural transformations and equivalences
• Formal verification of GALS systems
• Formal methods for analysis of GALS systems
• Hardware compilation of GALS system
• Latency-insensitive synchronous systems
• Mixed synchronous-asynchronous systems
• Synchronous/asynchronous interaction
• Clocking, interconnect and interface issues
• Interfaces between multiple timing domains
• System decomposition into GALS architectures
• Formal aspects of SoC and NoC design
• Case studies, comparisons and applications

The proceedings of the workshop will be published with Elsevier's Electronic Notes in Theoretical Computer Science (ENTCS).
Website: http://memocode.irisa.fr/FMGALS09/