DATE 2009

W4 Diagnostic Services in Network-on-Chips (DSNOC’09)

Date: 
Fri, 2009-04-24
Time: 
08:30 - 17:00
Location / Room: 
Uranie, Level 3

Organisers:
Nicola Nicolici, McMaster University, CA
Axel Jantsch, Royal Institute of Technology, SE
Thilo Piontech, University of Luebeck, DE
Erika Cota, Federal University of Rio Grande do Sul, BR 

Description: 
Network-on-Chips (NoCs) are emerging as a new on-chip communication paradigm. Diagnostic service, such as test, debug, and on-line monitoring, are becoming an important factor in designing next-generation NoC-based systems.  The NoC infrastructure itself requires diagnostic services, and can also be used to support those for the entire system.  Although significant research has been done in NoC design, there are many open and pressing issues regarding diagnostic services  The focus of this workshop is to explore them and their implications on system design.

0830 Welcome and Introduction
Keynote Address: “Robust System Design: What Diagnostic Services Do We Need to Overcome Reliability and Validation Challenges”
Subhasish Mitra, Stanford University, US
0930

Invited Talk
"Dependability Mechanisms in the Time-Triggered System-on-Chip (TTSoC)"
Hermann Kopetz, TU Vienna, AT

1030 BREAK & POSTER SESSION
Posters (see below) – combined with coffee + tea break
1100

Presentation Session
Presentations selected from regular paper submissions

"Dual NI Architectures for Fault Tolerant NoC"
Ville Rantala, Teijo Lehtonen, Pasi Liljebert and Juha Plosila, University of Turku, FI

"A High Level Methodology for Monitoring Network-on-Chips"
Paolo R Grassi, Marco Santambrogio, Christoph Puttmann, Christoper Pohl and Mario Pormann, Politecnico di Milano, IT and University of Paderborn, DE

"Hierarchical Agent Monitoring Services on Reconfigurable NoC Platform: A Formal Approach"
Liang Guang, Juha Plosila, Jouni Isoaho and Hannu Tenhunen, University of Turku, FI

"A New Fault-tolerant Routing Based on Turn Model for Network-on-Chip"
Yinhe Han and Binzhang Fu, Chinese Academy of Sciences, CN

1230 LUNCH
1330

Special Session: “Runtime reconfiguration for diagnostic services in NoCs”

Organizer: 
Thilo Pionteck, University of Luebeck, DE

Invited Speakers:
Roland Weigand, European Space Agency, NL
Christophe Boda, University of Potsdam, DE
Jose Nunez-Yanez, University of Bristol, UK
Juanjo Noguera, Xilinx, IE

1530

BREAK & POSTER SESSION

"Scheduling Framework for Dependable NoC-Based Systems"
Mihkel Tagel, Peeter Ellervee and Gert Jervan, TU Tallinn, EE

"Towards a Remote Monitoring and Testing of System-on-Chips"
O Laouamri and C Aktouf, DeFacTo Technologies, FR

"A Performance-Aware Fault-Tolerant Routing for NoC Design"
Arshin Rezazadeh, Mahmood Fathy and Rashin Rezazadeh, Iran University of Science & Technology, IR

"Generalization of Network-on-Chip Communication Modelling"
Peeter Ellervee, Mihkel Tagel and Gert Jervan, TU Tallinn, EE

"Providing Infrastructure Support to Assist NoC Software Development"
Bojan Mihajlovic, M H Neishaburi, Jason G Tong,
Nathaniel Azuelos, Zeljko Zilic and Warren J Gross,
McGill University, CA

"Fault Isolation with Intermediate Checks of End-to-End Checksums in the Time-Triggered System-on-Chip Architecture"
H Paulitsch, C Paukovits, C El Salloum and H Kopetz,
TU Vienna, AT

"Test Strategy Network-on-Chip Supporting Unicast-Multicast Data Transport"
Faizal A Samman, Thomas Hollstein and Manfred Glesner,
TU Darmstadt, DE

"Error Control Coding and Fault Mapping Models for Hybrid Electro-Optical Networks-on-Chips"
James S Guido and Alex Yakovlev, Newcastle University, UK

"Analysis of Fault Tolerant Deadlock-Free Routing Algorithms for Mesh NoCs"
Teijo Lehonten, Pasi Liljeberg and Juha Plosila,
University of Turku, FI

"Adaptive Health Monitoring in a Reconfigurable Network-on-Chip"
R Koch, C Albrecht and T Pionteck, University of Luebeck, DE

"Improving Reliability in NoCs with a Reconfigurable Router"
Caroline Concatto, Debora Matos, Luigi Carro, Érika Cota,
Fernanda Kastensmidt and Altamiro Susin, UFRGS, BR

1600 Panel Session: 
 “NoC: catalyzer or burden for validation and debug of future systems?”
Organizer: 
Érika Cota, UFRGS, BR
Moderator: 
Rob Aitken, ARM, US
Panelists:
Bart Vermeulen, NXP, NL
Philippe Martin, Arteris, FR
Zeljko Zilic, McGill University, CA
Marcello Coppola, STMicroelectronics, FR
1700 CLOSE