Organisers:
Juergen Teich, University of Erlangen-Nuernberg, DE
Daniel Gajski, University of California Irvine, US
Florian Schaefer, Cadence Design Systems, DE
Description:
As high-level synthesis is on its way to become widely accepted to increase productivity of industrial design flows, the EDA community has to face the new challenges of future Electronic System Level (ESL) synthesis. Nowadays, ESL design is a commonly accepted acronym used in the context of modeling and simulation. However, neglecting synthesis as a major part in the design flow will result in an enormous implementation gap between ESL and established hardware and embedded software design flows. Bridging this implementation gap manually seems prohibitive due to future application/implementation complexities. Although ESL synthesis has been announced by many roadmaps and companies, still there is no solution available or at least a common sense on what ESL synthesis could or should be.
The aim of the workshop is to help forming an understanding of the necessities of future ESL methodologies and tools by bringing together potential users, tool vendors, and research institutes. Questions to be addressed during the workshop are:
In this workshop, different points of view will be discussed by
At the heart of this workshop, there will be a panel discussion focusing on the question: Will there be a market for ESL synthesis tools and, if yes, what are the requirements for such tools?
Who should attend?
This Friday Workshop gives an extensive overview on research directions in ESL synthesis, forthcoming ideas in EDA synthesis tools, and design approaches used by companies. The workshop is targeted to researchers and professionals who want to get an insight in future design methodologies as well as managers who want to acquire a basic knowledge on ESL synthesis.
| 0900 | Welcome and Introduction |
| 0910 |
A User Perspective on ESL Synthesis 9:10 Pierre Paulin, STMicroelectronics, CA Bridging the ESL Synthesis Gap with Platform Programming Models 9:35 Bernhard Niemann, Fraunhofer IIS, DE C-Based System Synthesis - Myth or Reality? |
| 1000 | Break |
| 1020 |
Current Research Activities in ESL Synthesis HW-SW Cosynthesis from SDF Specification in PeaCE 10:45 Todor Stefanov, University of Leiden, NL Daedalus: Making System-Level Design Take Off 11:10 Samar Abdi, University of California Irvine, CA, US TLM Based Design of Multicore Embedded Systems with ESE 11:35 Christian Haubelt, University of Erlangen-Nuernberg, DE SystemCoDesigner: ESL Synthesis from SystemC Behavioral Models |
| 1200 | Lunch |
| 1300 |
New EDA Trends towards ESL Synthesis Hardware and Software Implementation from System-Level Models 13:25 Michael Meredith, Forte Design Systems Getting out My Crystal Ball: Trends in HLS for 2009-2010 13:50 Luciano Lavagno, Cadence Design Systems An ESL-to-GDSII design flow for Intellectual Property creation, optimization and reuse 14:15 Grant Martin, Tensilica, Inc The Future of ESL Synthesis - Only where necessary, not where possible |
| 1440 | Break |
| 1510 | Panel: Will ESL Synthesis Tools ever become good enough? Pierre Paulin, STMicroelectronics Ahmed Jerraya, CEA- LETI Michael McNamara, Cadence Design Systems Rolf Ernst, TU Braunschweig Grant Martin, Tensilica, Inc. Bart Kienhuis, Compaan Design B. V. |
| 1625 | Closing Remarks |
| 1630 | CLOSE |