KPASSA: A Tool for Simulating Periodically Scheduled SoCs
Julien Boucaron, Anthony Coadou, Robert de Simone
INRIA Sophia Antipolis - France

LIFTING: an Open-Source Logic Simulator
A. Bosio, G. Di Natale
Univeristy of Montpellier II - France

Asynchronous High-Speed Modeling and Optimization tool Set (AHMOSE)
Eslam Yahya, Laurent Fesquet, Marc Renaudin
INPG - France + TIEMPO sas - France

APRICOT: High-Level DD based Verification Framework
Maksim Jenihhin, Jaan Raik, Anton Chepurov, Taavi Viilukas, Raimund Ubar
Tallinn University of Technology - Estonia

FormED: A Formal Environment for Debugging
Andre Suelflow, Robert Wille, Christian Genz, Goerschwin Fey, Rolf Drechsler
University of Bremen - Germany

SPR Tool: Signal Reliability Analysis of Logic Circuits
Denis T. Franco, Maí C. Vasconcelos, Lirida Naviner, Jean-François Naviner
Federal University of Rio Grande - Brazil + Telecom ParisTech - France

UT Assertion Based Verification Package
Amirali Ghofrani, Fatemeh Javaheri, Hasan Sohofi, Zainalabedin Navabi
University of Tehran - Iran