Power minimisation is becoming a major design goal for systems implemented using Field Programmable Gate Arrays (FPGAs).  The two main contributions to FPGA power consumption are: due to the intrinsic FPGA micro-architecture and silicon implementation, and how designers implement applications on FPGAs including the design techniques applied and the particular CAD tools used.  This tutorial addresses the second category, i.e. those aspects a designer can influence and covers power-aware best design practices targeting currently available modern FPGAs.

The tutorial covers the basics of why FPGA power consumption is important and explains the sources of power consumption in modern FPGAs. The focus of this tutorial is to describe power optimised FPGA design techniques at multiple levels: (1) circuit and architecture design techniques; (2) back-end CAD tools (e.g., synthesis and place & route); and (3) front-end CAD tools (e.g., HW/SW partitioning and partial reconfiguration).  Finally, the tutorial introduces domain-specific languages as a research topic to facilitate the programmability of FPGAs and describe how FPGAs can achieve a competitive power advantage when compared to other programmable platforms (e.g., DSP and NPU) in different application domains (e.g., video and networking domains).  The presented power-aware FPGA design techniques are demonstrated using practical examples and experimental results.

The tutorial is addressed to hardware and system engineers as well as to researchers interested in FPGA power optimization.