Organiser:
Charles Chiang, Synopsys Inc., US
Speakers:
Louis Liu, TSMC, TW
Pol Marchal, IMEC, BE
Riko Radojcic, Qualcomm, US
Subarna Sinha, Synopsys Inc., US
Today’s SoCs/SiPs face numerous design challenges as increased integration of system components on a single die stretches the limits of technology and design capacity. 3D integration, where multiple dies are stacked and interconnected in the vertical dimension using through-silicon vias (TSVs), is probably the best hope for carrying ICs along (and even beyond) the path of Moore’s Law in the 21st century. However, successful adoption of 3D ICs by the semiconductor industry will require a killer application as well as modifications to design methodologies, EDA tools and manufacturing flows to enable 3D IC design. This tutorial will present the perspectives of industry leaders in design, manufacturing and EDA on the above-mentioned challenges and opportunities presented by 3D ICs.
Topics covered in this tutorial will include the architectural opportunities gained by designing in 3D, the technical challenges associated with the design and fabrication of such circuits, the “3D readiness” of the design, manufacturing and EDA sectors as well as the steps being undertaken by them towards commercial large scale use of 3D ICs. An overview of process technology aspects of 3D integration will be presented. Successful design of 3D ICs will require numerous changes to the current EDA tools as well as development of new tools. Concrete examples of new tools - such as technology tuning tools to co-optimise process technology and chip design requirements to define and validate the design enablement rules and models and architectural-level tools for co-exploring technology specifications and design options to define the optimum chip architecture for a given 3D process - will be described. A summary of the changes needed in key EDA stages as well as novel algorithms/methodologies for some of them will be presented. These include techniques for thermal modeling and algorithms for thermal-aware 3D floorplanning and a novel parasitic extraction methodology for 3D ICs. In addition, TCAD data for test structures for noise and reliability will also be presented.
The intended audience for this tutorial is EDA engineers who are interested to make their commercial tools “3D ready”, researchers looking for interesting relevant topics for research as well as designers looking to migrate their own designs into 3D.