Low power design under parameter variations has emerged as a major design challenge in the nanometre regime.  Design considerations for low power operation and variation tolerance typically impose contradictory requirements.  Low-power design techniques such as voltage scaling, dual-Vth assignment and gate sizing can have large negative impact on parametric yield under process variations.  Moreover, temporal parameter variations caused by temperature fluctuations or device degradations can adversely affect the reliability of low power designs.

This tutorial aims at providing comprehensive coverage on modelling, analysis and circuit/architecture level design methodology for low power and variation-tolerant logic circuits, memory and systems.  It will address temperature-aware design; dynamic adaptation to temperature variations and device degradations such as Negative Bias Temperature Instability (NBTI).  Post-silicon calibration and healing techniques using voltage scaling, adaptive body biasing or clock stretching will also be discussed.  Current industry practices along with industrial data on process variability, variability characterisation, modelling and mitigation techniques will be presented.

This tutorial is targeted towards practicing VLSI design engineers, technical managers, tool developers, researchers and students working in the area of low power and variation tolerant VLSI design.