DATE - Design, Automation and Test in Europe

D1 New Developments and Trends in Networks on Chip

Date: 
Mon, 2009-04-20
Time: 
09:30 - 13:00
Location / Room: 
Gallieni AB, Level 2

Organiser:
Marcello Coppola , STMicroelectronics, FR
Marcello Lajolo , NEC, US
Riccardo Localelli, STMicroelectronics, FR
Partha Kundu, INTEL, US
Pascal Vivet, CEA-LETI, FR

Networks on Chip (NoCs) are rapidly becoming the mainstream architectural paradigm to cope with backend issues and application requirements.  People attending this tutorial will discover the latest industrial developments in NoC design and short and long term research directions in SoC for consumer applications and multi-core/many-core systems.  This tutorial includes a short history on on-chip interconnects followed by three Industry presentations (ST, INTEL, NEC) and one Academic presentation (CEA-LETI).  We cover NoC design fundamentals, industry need and why the time is right for NoC design.

The tutorial is intended for engineers, managers, students, academics designers and managers who are interested to learn more about support technologies (SoC and massively parallel many-core architectures, communication-centric design, globally asynchronous and locally synchronous logic, programming languages and paradigms) that are necessary for realising the full potentials of NoC design.