DATE 2009

A System-Level Modelling, Analysis and Synthesis of Embedded Multi-Core Designs

Date: 
Mon, 2009-04-20
Time: 
09:30 - 18:00
Location / Room: 
Clio, Level 3

Organiser: 
Daniel D Gajski, CECS, UC Irvine, US

Speakers: 
Andreas Gerstlauer, UT Austin, US
Juergen Teich, University of Erlangen-Nuremberg, DE
Wolfgang Ecker, Infineon Technologies, DE
Samar Abdi, CECS, UC Irvine, US
Christian Haubelt, University of Erlangen-Nuremberg, DE
Mike Meredith, Forte Design Systems, US
Martin Speitel, Fraunhofer IIS, DE
Daniel D Gajski, CECS, UC Irvine, US

The continuous increase in size, complexity and heterogeneity of embedded system design has introduced new challenges in their modeling and implementation. Multi-core embedded system design requires high speed models for early validation and performance evaluation. As a result, electronic system level (ESL) modeling has moved up in abstraction from cycle accurate RTL to timed and untimed transaction-level models (TLMs), which are typically based on C or C++. However, the open question is how to get from a high level C based system description to a SW and HW implementation? The goal of this tutorial is to answer such questions and to provide system designers and managers with new insight into ESL modeling concepts and synthesis techniques so that they can drastically increase their productivity in the future.

In this tutorial, we will cover the key concepts and state of the art tools for C Based system design using industrial case studies such as MP3 player, JPEG encoder and digital radio designs. We will discuss TLM semantics for automatic model generation, methods for automatic design space exploration, and HW/SW synthesis.  We will also present new advances in commercial C to RTL techniques, and their integration within complete ESL modeling, exploration, and synthesis frameworks.

This tutorial is targeted towards embedded SW and HW developers, engineers who use or are interested in using ESL design tools, managers of system designers, and verification engineers.