Overview: 
Shrinking device feature sizes, increasing complexity, and demand for performance of modern digital ICs require faster clock rates and higher operating frequencies, in several cases exceeding the gigahertz range. Because of high-frequency square-waves rich in harmonics is distributed throughout the die, ICs are prolific generators of electromagnetic interference (EMI).

Strict governmental regulations and international standards, mainly in the automotive and
wireless domain, are driving new efforts towards design solutions for electromagnetic
compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit
and package designers. Even though constraints such as area, timing, and power consumption are satisfied, if the chip does not meet the EMC requirements, then the circuit has to be redesigned with a increasing NRE costs and subsequent production delays.
ST has developed an effective and practical EMC-aware design methodology, that’s seamlessly
integrated into the standard design flow, allows circuit designer to account for EMC requirements during the different phases of the physical implementation, and simulate the EMI behavior of the overall system including die, package, and PCB.

A critical enabler of this methodology is power noise analysis, modeling, and suppression. We
successfully used Apache’s RedHawk including MMX for analysis and CPM (Chip Power Model)
for generating a compact die representation. We connected CPM with package and PCM models to develop an EMI simulation flow, which allows us to accurately predict the circuit EMC behavior before tape-out. Experimental results obtained on a microcontroller for automotive applications demonstrate the effectiveness of our approach and of the Apache’s solution for low-EMI design.