Tuesday-At-A-Glance | DATE - Design, Automation and Test in Europe

Tuesday-At-A-Glance

Interactive Presentations (in Exhibition Hall Rhodes, Level 2): 1600 - 1630 IP1
Exhibition Break: 1030 - 1130
For Exhibition Theatre Details please click here.

Breaks: 1300 - 1430 (Lunch) / 1600 - 1700

Track	Room	0840 - 1030		1130 - 1300	1430 - 1600	1700 - 1830
1	Hermes, Level 2	Plenary Opening Remarks and Awards Keynote Addresses Room Athena, Level 2		2.1 EXECUTIVE SESSION – FPGA Developments: What is New?	3.1 EXECUTIVE SESSION – Are We There Yet? A Progress Report on the Move to 32nm	4.1 EXECUTIVE SESSION – Funding and New Ventures: What Can We Expect Now?
2	Clio, Level 3			2.2 Emerging Interconnection Technologies for Multicore	3.2 Variability and Reliability Aware Energy Management	4.2 Power Optimisations Including Reliability and Temperature
3	Gallieni 3, Level 2			2.3 Applications on Reconfigurable Hardware 1	3.3 Applications on Reconfigurable Hardware 2	4.3 Aerospace Systems, MEMS and Mixed-Signal Applications
4	Thalie, Level 3			2.4 Task Allocation for MPSoCs	3.4 EMBEDDED TUTORIAL – High-Level Modelling and Verification	4.4 PANEL SESSION – Is the Second Wave of HLS the One Industry Will Surf on?
5	Erato, Level 3			2.5 Advanced Approaches for Reliability Improvement	3.5 System-Level Test and Debug	4.5 Test for Variability, Reliability and Circuit Marginality
6	Uranie, Level 3			2.6 Scheduling and Timing Analysis for Embedded Real-Time Systems	3.6 Model-Based Design and HW/SW System Integration	4.6 System Approaches to Flash Memory Management
7	Gallieni AB, Level 2			2.7 System-Level Synthesis and Optimisation	3.7 NoC Customisation Techniques	4.7 Novel Design Space Exploration and Power Optimisation Techniques
8	Exhibition Theatre, Level 2			2.8 PANEL SESSION – Consolidation, a Modern “Moor of Venice” Tale	3.8 HOT TOPIC – Analogue Layout Synthesis – Light at the End of the Tunnel?	4.8 PANEL SESSION – Open Source Hardware IP, Are You Serious?

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