Overview: 
The realization of a modern Media Processing SoC is a very complex activity, with multiple design teams distributed across many countries. NXPs latest 45nm design contains >150 individual soft and hard IPs many of which were being developed concurrently with the host SoC.

All these design activities must converge predictably at tape-out time. With Time-to-Market such a crucial factor in today’s fast moving semiconductor business there is often no time for a re-spin.

During the definition phase, the Physical Design Team must underpin commitments on cost,
performance, area, package choice, IR-drop and the tape-out schedule. These commitments
must be made long before the IP content has matured into stable design.
The “traditional” approach is to use complex sign-off-tools that analyze detailed design data to ensure that the performance targets are met. But sign-off tools are run so late in the design process that if any significant problems are found, fixing them will result in schedule slip and potentially lost revenue.

Physical Design team used Apache’s RedHawk for early power planning and IR-drop analysis to define, model, and explore “what-if” scenarios of the power plan on NXP’s 45nm flip-chip design.

The tool was used to determine the optimum bump and ESD cell locations; define the power
mesh; and explore different macro placement options – all before any “real” design data was
available. Further incremental refinement was carried out as the design matured, so that when the SoC team reached the sign-off phase the IR-drop results were highly predictable and within specification.