9.7 Efficient Reduction of Cell and Interconnect Models
Date:
Thu, 2009-04-23Time:
08:30 - 10:00Location / Room:
Gallieni ABModerators:
W Schilders, NXP Semiconductors, NL
L Silveira, INESC ID / IST – TU Lisbon, PT
Papers in this section will present new techniques for improving the efficiency of cell and interconnect analysis and modelling. The first two papers discuss reduction and compression techniques for parameterised on-chip passives and library cell waveform computation. The remaining two papers describe practical improvements in interconnect roughness modelling and decoupling optimisation.
| 0830 | ON THE EFFICIENT REDUCTION OF COMPLETE EM BASED PARAMETRIC MODELS J Fernandez Villena, INESC ID / IST - TU Lisbon, PT G Ciuprina and D Ioan, Polytechnic U of Bucharest, CTRY??? L M Silveira, INESC ID / IST - TU Lisbon / Cadence Research Labs, PT |
| 0900 | EFFICIENT COMPRESSION AND HANDLING OF CURRENT SOURCE MODEL LIBRARY WAVEFORMS S Hatami and M Pedram, U of Southern California, US P Feldmann and S Abbaspour, IBM Corp, US |
| 0930 (S) | NEW SIMULATION METHODOLOGY OF 3D SURFACE ROUGHNESS LOSS FOR INTERCONNECTS MODELING Q Chen and N Wong, The U of Hong Kong, PRC |
| 0945 (S) | AN EFFICIENT DECOUPLING CAPACITANCE OPTIMIZATION USING PIECEWISE POLYNOMIAL MODELS X Wang and Y Cai, TsingHua U, Beijing, PRC S X-D Tan and J Relles, UC Riverside, US |
