9.4 Architectural Synthesis
Date:
Thu, 2009-04-23Time:
08:30 - 10:00Location / Room:
Thalie, Level 3Moderators:
P Ienne, EPF Lausanne, CH
R Kastner, UC San Diego, US
Architectural of digital systems, covering word-length optimisation, high-level synthesis of latch-based and single-event upset tolerant circuits, and special purpose permutation architectures.
| 0830 | FINITE PRECISION BIT-WIDTH ALLOCATION USING SAT-MODULO THEORY A B Kinsman and N Nicolici, McMaster University, CA |
| 0900 | HLS-L: HIGH-LEVEL SYNTHESIS OF HIGH PERFORMANCE LATCH-BASED CIRCUITS S Paik, I Shin and Y Shin, Korea Advanced Institute of Science And Technology (KAIST), KR |
| 0930 (S) | AUTOMATIC GENERATION OF STREAMING DATAPATHS FOR ARBITRARY FIXED PERMUTATIONS P A Milder, J C Hoe and M Pueschel, Carnegie Mellon U, US |
| 0945 (S) | SEU-AWARE RESOURCE BINDING FOR MODULAR REDUNDANCY BASED DESIGNS ON FPGAs S Golshan and E Bozorgzadeh, UC Irvine, US |
