4.5 Test for Variability, Reliability and Circuit Marginality
Date:
Tue, 2009-04-21Time:
17:00 - 18:30Location / Room:
Erato, Level 3Moderators:
A Rubio, UP Catalunya, ES
E J Marinissen, IMEC, BE
Papers in this session describe statistical characterisation of process variation, test for adjusting post-silicon tuning buffers, variability based yield prediction, impact of voltage scaling on SRAM reliability and mitigating IR-drop effects during testing.
| 1700 | ANALYZING THE IMPACT OF PROCESS VARIATIONS ON PARAMETRIC MEASUREMENTS: NOVEL MODELS AND APPLICATIONS S Reda, Brown U, US S Nassif, IBM Research, US |
| 1730 | ON LINEWIDTH-BASED YIELD ANALYSIS FOR NANOMETER LITHOGRAPHY A Sreedhar and S Kundu, Massachusetts U, Amherst, US |
| 1800 | IMPACT OF VOLTAGE SCALING ON NANOSCALE SRAM RELIABILITY V Chandra and R Aitken, ARM, US |
