4.2 Power Optimisations Including Reliability and Temperature
Date:
Tue, 2009-04-21Time:
17:00 - 18:30Location / Room:
Clio, Level 3Moderators:
V Mooney III, Georgia Institute of Technology, US
J Henkel, Karlsruhe U, DE
This session presents three papers dealing with optimising power consumption and its consequences. The first paper presents a technique to simultaneously optimise for leakage and aging effects, the second paper optimises through a concurrent clock and power gating approach whereas the last paper optimises for reliability induced by temperature.
| 1700 | GATE REPLACEMENT TECHNIQUES FOR SIMULTANEOUS LEAKAGE AND AGING OPTIMIZATION Y Wang, X Chen, W Wang, Y Cao, Y Xie, H Yang, Y Wang, X Chen and H Yang, Tsinghua U, PRC W Wang and Y Cao, Arizona State U, US Y Xie, Penn. State U, US |
| 1730 | CONCURRENT CLOCK AND POWER GATING IN AN INDUSTRIAL DESIGN FLOW L Bolzani, A Calimera, A Macii, E Macii and M Poncino, Politecnico di Torino, IT |
| 1800 | TRAM: A TOOL FOR TEMPERATURE AND RELIABILITY AWARE MEMORY DESIGN A Khajeh, A Gupta, N Dutt, F Kurdahi and A Eltawil, UC Irvine, US |
