Due to increasing functional complexity of SoC, the difficulties in analogue design and the lack of support for analogue circuits increase the bottleneck of analogue components in chip design.  Eminently critical is the layout synthesis part of the design flow.  Although there have been very good works from academia over the years, some of which even found their way to commercial EDA tools, industrial application of analogue layout synthesis is still in its infancy compared to its digital counterpart.  But it seems that this situation is about to change: interoperable library alliances for layout transfer between platforms are initiated, EDA start-ups as well as major leaders are announcing new automated layout tools.  In this exciting scenario, academia continues to strive for new approaches to analogue layout and has recently produced some interesting new solutions.  This session first gives a tutorial on important features of these solutions, namely:  hierarchical circuit clustering, layout-aware synthesis, and enhanced shape functions for deterministic analogue placement.  In the second part, we will discuss the advances in analogue layout synthesis and their potential impact in a panel with designers and CAD vendors.  Key issues are expected to be discussed, such as the reasons for the low dissemination of analogue layout methods in industry, the requirements of industrial representatives on practicable tools, and the future of analogue layout synthesis.