3.5 System-Level Test and Debug
Date:
Tue, 2009-04-21Time:
14:30 - 16:00Location / Room:
Erato, Level 3Moderators:
F Novak, Josef Stefan Institute, SI
V Singh, Indian Institute of Science, IN
This session covers novel approaches to debug and test. In particular, the papers deal with transaction-level debug, compression of debug data, fault emulation in an automotive context, and test infrastructure design for 3D stacked dies.
| 1430 | A HIGH-LEVEL DEBUG ENVIRONMENT FOR COMMUNICATION-CENTRIC DEBUG K Goossens, NXP Semiconductors and TU Delft, NL B Vermeulen, NXP Semiconductors, NL A B Nejad, KTH, SE |
| 1500 | CACHE AWARE COMPRESSION FOR PROCESSOR DEBUG SUPPORT A Vishnoi, P R Panda and M Balakrishnan, Indian Institute of Technology Delhi, IN |
| 1530 (S) | FAULT INSERTION TESTING OF A NOVEL CPLD-BASED FAILSAFE SYSTEM G Griessnig, AVL List, AT R Mader, C Steger and R Weiss; TU Graz, AT |
| 1545 (S) | TEST ARCHITECTURE DESIGN AND OPTIMIZATION FOR THREE-DIMENSIONAL SoCs L Jiang, L Huang and Q Xu, The Chinese U of Hong Kong, HK |
