3.3 Applications on Reconfigurable Hardware 2
Date:
Tue, 2009-04-21Time:
14:30 - 16:00Location / Room:
Gallieni 3, Level 2Moderators:
R Cottrell, Altera European Technology Centre
C Heer, Infineon Technologies, DE
Applications, architectures and design methods for reconfigurable hardware.
| 1430 | DESIGN AND IMPLEMENTATION OF A DATABASE FILTER FOR BLAST ACCELERATION P Afratis, C Galanakis, E Sotiriades, G-G Mplemenos, G Chrysos, Y Papaefstathiou and D Pnevmatikatos, TU Crete, GR |
| 1500 | A SOFTWARE-SUPPORTED METHODOLOGY FOR EXPLORING INTERCONNECTION ARCHITECTURES TARGETING 3-D FPGAS K Siozios and D Soudris, Democritus U of Thrace, GR |
| 1530 (S) | PRIORITY-BASED PACKET COMMUNICATION ON A BUS-SHAPED STRUCTURE FOR FPGA-SYSTEMS O Sander, B Glas, C Roth, J Becker and K D Mueller, KIT, DE |
| 1545 (S) | EXPLORATION OF POWER REDUCTION AND PERFORMANCE ENHANCEMENT IN LEON3 PROCESSOR WITH ESL REPROGRAMMABLE EFPGA IN PROCESSOR PIPELINE AND AS A CO-PROCESSOR S Z Ahmed, MENTA/LIRMM, FR J Eydoux and L Rouge, MENTA, FR G Sassatelli and L Torres, CNRS/LIRMM/UM2, FR |
