In spite of the technical and, more recently, economic challenges, significant efforts are been spent developing the next CMOS node, 32nm.  It seems only yesterday that we worried about the challenges of 45nm and excited about the promise of a multitude of benefits – and now we face the 32nm process.  So, how are we doing with this process?  Has anyone really designed anything beyond test chips?  Are the EDA tools ready for the complexity of the design rules?  What do we need beyond the current DFM?  Will we get the yield – if not now, when?  What is the minimum volume necessary for making it a viable technology?  Will we have more than two foundries?  The panelists will share their experience by enumerating many of the challenges, potential solutions and their specific observations based on current knowledge.