2.7 System-Level Synthesis and Optimisation
Date:
Tue, 2009-04-21Time:
11:30 - 13:00Location / Room:
Gallieni AB, Level 2Moderators:
P Pop, TU Denmark, DK
R Woods, Queens U Belfast, IE
This session deals with the generation of systems at a high level of abstraction. Two papers are on design space exploration for the protocol converter problem. Another paper deals with the optimization of data flow graphs to minimise hardware implementation and the last paper is on the synthesis of multimedia applications, addressing the optimisation of buffer size.
| 1130 | OPTIMIZING DATA FLOW GRAPHS TO MINIMIZE HARDWARE IMPLEMENTATION D Gomez-Prado, Q Ren and M Ciesielski, Massachusetts U, US J Guillot and E Boutillon, LESTER, Bretagne Sud U, FR |
| 1200 | MULTI-CLOCK SoC DESIGN USING PROTOCOL CONVERSION R Sinha, P S Roop, Z Salcic, Auckland U, AU S Basu, Iowa State U, US |
| 1230 (S) | A FORMAL APPROACH TO DESIGN SPACE EXPLORATION OF PROTOCOL CONVERTERS K Avnit and A Sowmya, New South Wales U, AU |
| 1245 (S) | MODEL-BASED SYNTHESIS AND OPTIMIZATION OF STATIC MULTI-RATE IMAGE PROCESSING ALGORITHMS J Keinert, Fraunhofer IIS, Erlangen, DE H Dutta, F Hannig, C Haubelt and J Teich, Erlangen-Nuremberg U, DE |
